Abstract: The present invention relates to a full analog phase shifter, and more particularly, comprises: a variable switch panel comprising a first conductive pattern terminal and a second conductive pattern terminal; and a pattern PCB on which a plurality of array antenna elements are arranged and a transmission line at which the first conductive pattern terminal and the second conductive pattern terminal come into contact is pattern-printed, wherein, assuming that two variable switch panels are disposed in the vertical direction, the two variable switch panels are provided as a slider type that slides in the vertical direction so that, due to a phase shift caused by the contact between the first conductive pattern terminal and the second conductive pattern terminal and the transmission line, phases of the plurality of array antenna elements are linearly distributed on a same reference phase plane, thereby providing the advantage of easily implementing a mirror symmetry structure having a linear phase distribution on

Abstract: Provided is a method and device for identifying a vehicle through data and wireless signal analysis, including: a sensor module for recognizing a vehicle; a camera for capturing an image of the exterior of the vehicle; an antenna; a wireless communication unit for receiving, via the antenna, a wireless signal transmitted by a wireless radio wave transmitter mounted or loaded on the vehicle; and a control unit which extracts a first identification value by analyzing sensing data sensed by the sensor module or the image captured using the camera, and which extracts a second identification value by analyzing the wireless signal received by the wireless communication unit, and which identifies the vehicle on the basis of the first identification value and second identification value.

Abstract: Provided is a biopsy instrument having an outer needle-locking member, which is capable of checking whether an inner needle is placed in target tissue and shooting an outer needle after the tissue is sufficiently introduced into the inner needle, thereby accurately collecting the target tissue that is to be.

Abstract: The present invention relates to a method and a device for identifying a vehicle through an image and wireless signal analysis, the device comprising: an infrared camera for capturing the appearance of a vehicle while irradiating the vehicle with infrared rays having different wavelength bands from each other; an antenna; a wireless communication unit for receiving, through the antenna, a wireless signal transmitted from a wireless communication device mounted or loaded on the vehicle; a storage unit for storing an infrared image captured by the infrared camera, and the wireless signal received through the wireless communication unit; and a control unit for extracting a first identification value by analyzing the infrared image stored in the storage unit, extracting a second identification value by analyzing the wireless signal stored in the storage unit, and identifying the vehicle on the basis of the first identification value and the second identification value.

Abstract: Provided is a biopsy instrument having an outer needle-locking member, which is capable of checking whether an inner needle is placed in target tissue and shooting an outer needle after the tissue is sufficiently introduced into the inner needle, thereby accurately collecting the target tissue that is to be.

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming a second insulation pattern on a first insulation pattern. The first insulation pattern may cover a plurality of conductive structures, and may include a hole therein. The second insulation pattern may include a trench therein that is connected with the hole. The methods may also include forming a spacer on sidewalls of the hole and the trench. The methods may further include forming a wiring structure in the hole and the trench.

Abstract: The present disclosure relates to an apparatus and a method of setting a gesture in an electronic device. The method includes: when a specific gesture is selected among a plurality of gestures, displaying a gesture setting region for receiving an input of the specific gesture; generating and storing gesture information about the specific gesture when the specific gesture is input through the gesture setting region; and setting a recognition reference of the specific gesture based on the gesture information. Further, a technology for setting a gesture in an electronic device may be variously implemented through the various example embodiments of the present disclosure.

Abstract: The present invention relates to cinchona-based bifunctional organocatalysts and methods for preparing chiral hemiesters using the same. More specifically, the present invention relates to methods for preparing chiral hemiesters from prochiral or meso cyclic acid anhydrides via desymmetrization, using bifunctional cinchona alkaloid catalysts comprising sulfonamide functional groups.

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming a second insulation pattern on a first insulation pattern. The first insulation pattern may cover a plurality of conductive structures, and may include a hole therein. The second insulation pattern may include a trench therein that is connected with the hole. The methods may also include forming a spacer on sidewalls of the hole and the trench. The methods may further include forming a wiring structure in the hole and the trench.

Abstract: The present invention relates to cinchona-based bifunctional organocatalysts and methods for preparing chiral hemiesters using the same. More specifically, the present invention relates to methods for preparing chiral hemiesters from prochiral or meso cyclic acid anhydrides via desymmetrization, using bifunctional cinchona alkaloid catalysts comprising sulfonamide functional groups.

Abstract: Provided is a method of forming a semiconductor device. A tunnel insulating layer is formed on a substrate having a cell region and a low voltage region. First and second charge storage gate patterns (e.g., floating gate patterns) are formed on the tunnel insulating layers of the cell and low voltage region, respectively. A blocking insulating layer and a control gate conductive layer are formed on the substrate in sequence. The control gate conductive layer, the blocking insulating layer, the second floating gate pattern and the tunnel insulating layer of the low voltage region are removed to expose the substrate of the low voltage region. The low-voltage gate insulating layer is formed on the exposed substrate. A low-voltage gate conductive pattern is formed on the low-voltage gate insulating layer.

Abstract: Disclosed is a variable phase shifter The variable phase shifter includes a housing; a fixed board unit fixedly installed inside the housing, equipped with an input microstrip line with a via hole for receiving an input signal on one face thereof, and equipped with at least one circular arc-shaped output microstrip line outside the input microstrip line; and a rotating board unit rotatably installed inside the housing while being in contact with the one face of the fixed board unit, equipped with a transmission microstrip line on a face coming in contact with the one face of the fixed board unit, and for providing at least one output signal by making coupling even during rotation thereof.

Abstract: Semiconductor integrated circuit devices having SRAM cells and flash memory cells are provided. The devices include an integrated circuit substrate having an SRAM cell region, a flash memory cell region and a logic circuit region. An isolation layer is provided in a predetermined region of the substrate. The isolation layer defines a SRAM cell active region, a flash memory cell active region and a logic transistor active region in the SRAM cell region, the flash memory cell region and the logic circuit region, respectively. An SRAM cell gate pattern crosses over the SRAM cell active region. The SRAM cell gate pattern includes a main gate electrode and a dummy gate electrode which are sequentially stacked. A flash memory cell gate pattern crosses over the flash memory cell active region.

Abstract: Provided is a method of forming a semiconductor device. A tunnel insulating layer is formed on a substrate having a cell region and a low voltage region. First and second charge storage gate patterns (e.g., floating gate patterns) are formed on the tunnel insulating layers of the cell and low voltage region, respectively. A blocking insulating layer and a control gate conductive layer are formed on the substrate in sequence. The control gate conductive layer, the blocking insulating layer, the second floating gate pattern and the tunnel insulating layer of the low voltage region are removed to expose the substrate of the low voltage region. The low-voltage gate insulating layer is formed on the exposed substrate. A low-voltage gate conductive pattern is formed on the low-voltage gate insulating layer.

Abstract: Semiconductor integrated circuit devices having SRAM cells and flash memory cells are provided. The devices include an integrated circuit substrate having an SRAM cell region, a flash memory cell region and a logic circuit region. An isolation layer is provided in a predetermined region of the substrate. The isolation layer defines a SRAM cell active region, a flash memory cell active region and a logic transistor active region in the SRAM cell region, the flash memory cell region and the logic circuit region, respectively. An SRAM cell gate pattern crosses over the SRAM cell active region. The SRAM cell gate pattern includes a main gate electrode and a dummy gate electrode which are sequentially stacked. A flash memory cell gate pattern crosses over the flash memory cell active region.

Abstract: A borderless contact structure and method of forming thereof are provided. A device isolation region having a protrusion is formed at a predetermined region of a semiconductor substrate. The top surface of the protrusion is higher in level than that of the semiconductor substrate. An impurity diffusion region is formed in an active region surrounded by the device isolation region. An etch stop spacer is formed on a sidewall of the protrusion. An etch stop layer and an interlayer insulating layer are sequentially formed on the resultant structure including the impurity diffusion region, the device isolation region and the etch stop spacer. A contact hole opening the interlayer insulating layer and the etch stop layer is formed to expose at least a portion of the impurity diffusion region.

Abstract: A full CMOS SRAM cell includes first and second active regions formed in a semiconductor substrate. A word line traverses first and second areas of the second active region, and first and second gate electrodes are arranged to be perpendicular to the word line. The first and second gate electrodes are parallel to each other and traverse the first and second active regions, respectively. A power line is electrically connected to a first common source region and is arranged parallel to the word line, the first common source region being the first active region between the first gate electrode and the second gate electrode. A ground line is electrically connected to a second common source region and is arranged parallel to the word line, the second common source region being the second active region between the first gate electrode and the second gate electrode. First and second bit lines are arranged to be perpendicular to the word line and parallel to each other.

Abstract: A full CMOS SRAM cell includes first and second active regions formed in a semiconductor substrate. A word line traverses first and second areas of the second active region, and first and second gate electrodes are arranged to be perpendicular to the word line. The first and second gate electrodes are parallel to each other and traverse the first and second active regions, respectively. A power line is electrically connected to a first common source region and is arranged parallel to the word line, the first common source region being the first active region between the first gate electrode and the second gate electrode. A ground line is electrically connected to a second common source region and is arranged parallel to the word line, the second common source region being the second active region between the first gate electrode and the second gate electrode. First and second bit lines are arranged to be perpendicular to the word line and parallel to each other.

Abstract: A full CMOS SRAM cell includes first and second active regions formed in a semiconductor substrate. A word line traverses first and second areas of the second active region, and first and second gate electrodes are arranged to be perpendicular to the word line. The first and second gate electrodes are parallel to each other and traverse the first and second active regions, respectively. A power line is electrically connected to a first common source region and is arranged parallel to the word line, the first common source region being the first active region between the first gate electrode and the second gate electrode. A ground line is electrically connected to a second common source region and is arranged parallel to the word line, the second common source region being the second active region between the first gate electrode and the second gate electrode. First and second bit lines are arranged to be perpendicular to the word line and parallel to each other.

Abstract: A full CMOS SRAM cell is provided. The SRAM cell includes first and second active regions formed on a semiconductor substrate, arranged parallel to each other. A third active region is formed on the semiconductor substrate between the first active region and the second active region parallel to the first active region, and a fourth active region is formed on the semiconductor substrate between the third active region and the second active region parallel to the second active region. A word line intersects the first and second active regions. A first common conductive electrode intersects the first active region and the third active region, and a second common conductive electrode intersects the second active region and the fourth active region.