Abstract: A foldable display is disclosed. In one aspect, the foldable display includes a first display unit located on a front surface of the foldable display, a second display unit located on a first side surface of the foldable display, and a third display unit located on a second side surface of the foldable display. The foldable display includes a first configuration in which the first to third display units are exposed and a second configuration in which the first display unit is folded and the second and third display units are exposed. The second and third display units are configured to form a fourth display unit inclined with respect to the folded first display unit in the second configuration of the foldable display.

Abstract: A foldable display is disclosed. In one aspect, the foldable display includes a first display unit located on a front surface of the foldable display, a second display unit located on a first side surface of the foldable display, and a third display unit located on a second side surface of the foldable display. The foldable display includes a first configuration in which the first to third display units are exposed and a second configuration in which the first display unit is folded and the second and third display units are exposed. The second and third display units are configured to form a fourth display unit inclined with respect to the folded first display unit in the second configuration of the foldable display.

Abstract: A foldable display is disclosed. In one aspect, the foldable display includes a first display unit located on a front surface of the foldable display, a second display unit located on a first side surface of the foldable display, and a third display unit located on a second side surface of the foldable display. The foldable display includes a first configuration in which the first to third display units are exposed and a second configuration in which the first display unit is folded and the second and third display units are exposed. The second and third display units are configured to form a fourth display unit inclined with respect to the folded first display unit in the second configuration of the foldable display.

Abstract: A foldable display is disclosed. In one aspect, the foldable display includes a first display unit located on a front surface of the foldable display, a second display unit located on a first side surface of the foldable display, and a third display unit located on a second side surface of the foldable display. The foldable display includes a first configuration in which the first to third display units are exposed and a second configuration in which the first display unit is folded and the second and third display units are exposed. The second and third display units are configured to form a fourth display unit inclined with respect to the folded first display unit in the second configuration of the foldable display.

Abstract: A display device is disclosed. The display device includes: a plurality of pixels; a memory storing a lookup table including compensation values for pixels at specific locations of the display. The lookup table also stores compensation values obtained by a bilinear compensation method. The display also includes a data compensator calculating the compensation values corresponding to a location where an image signal is displayed using the compensation values and substitution values stored in the lookup table. The substitution values are obtained by bit-shifting the compensation values acquired by bilinear compensation method. The display device avoids the need to use large and slow divider circuits used in ICs implementing bilinear compensation method.

Abstract: A foldable display is disclosed. In one aspect, the foldable display includes a first display unit located on a front surface of the foldable display, a second display unit located on a first side surface of the foldable display, and a third display unit located on a second side surface of the foldable display. The foldable display includes a first configuration in which the first to third display units are exposed and a second configuration in which the first display unit is folded and the second and third display units are exposed. The second and third display units are configured to form a fourth display unit inclined with respect to the folded first display unit in the second configuration of the foldable display.

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: A foldable display is disclosed. In one aspect, the foldable display includes a first display unit located on a front surface of the foldable display, a second display unit located on a first side surface of the foldable display, and a third display unit located on a second side surface of the foldable display. The foldable display includes a first configuration in which the first to third display units are exposed and a second configuration in which the first display unit is folded and the second and third display units are exposed. The second and third display units are configured to form a fourth display unit inclined with respect to the folded first display unit in the second configuration of the foldable display.

Abstract: A display device is disclosed. The display device includes: a plurality of pixels; a memory storing a lookup table including compensation values for pixels at specific locations of the display. The lookup table also stores compensation values obtained by a bilinear compensation method. The display also includes a data compensator calculating the compensation values corresponding to a location where an image signal is displayed using the compensation values and substitution values stored in the lookup table. The substitution values are obtained by bit-shifting the compensation values acquired by bilinear compensation method. The display device avoids the need to use large and slow divider circuits used in ICs implementing bilinear compensation method.

Abstract: A method of processing data including dividing, at a transmitter, data into 3-bit units, generating, at the transmitter, first and second clock embedded data signals and a third data signal, wherein a clock signal and first bits of the units are included in the first clock embedded data signal, the clock signal and second bits of the units are included in the second clock embedded data signal and third bits of the units are included in the third data signal, transmitting, from the transmitter to a receiver, the first and second clock embedded data signals and the third data signal, and restoring, at the receiver, the first and second bits and the clock signal from the first and second clock embedded data signals and the third bits from the third data signal.

Abstract: Embodiments relate to a method of decomposing a layout of a semiconductor device. The method may include generating a pattern layout including first patterns and second patterns, generating an interference map for the pattern layout, the interference map including optical interference information regarding the first and second patterns, and decomposing the pattern layout into a first decomposition pattern layout including the first patterns, and a second decomposition pattern layout including the second patterns, based on the interference map. In the interference map, an influence of constructive interference on the first patterns may be greater than an influence of constructive interference on the second patterns.

Abstract: An image signal modifying device includes a pixel, a memory which stores compressed information in which a three-dimensional (“3-D”) lookup table is coded, an image signal modifying unit which decodes the compressed information to generate a restored 3-D lookup table and generates a modified signal based on a first image signal of a first frame, a second image signal of a second frame, a third image signal of a third frame and the restored 3-D lookup table, and a data driver which converts the modified signal into the data voltage and supplies the data voltage to the pixel.

Abstract: A latency control circuit includes a clock delay configured to output a plurality of serial delay signals obtained by serially delaying an input clock signal with the same intervals, a deviation information generating unit configured to generate a deviation information on the basis of a delay value, which the clock signal undergoes in a chip, and latency information, a clock selector configured to output a plurality of clock selection signals based on the plurality of serial delay signals and the deviation information, a command signal processing unit configured to generate a read signal based on an input command signal, and output a variable delay duplication signal by variably delaying the read signal, and a latency shifter configured to output a latency signal by combining the plurality of clock selection signals with the variable delay duplication signal.

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: Apparatus and method for detecting insertion of an external audio outputting device in an electronic device. The apparatus comprises an earphone socket into which the external audio outputting device is inserted. The earphone socket includes first and second terminal sets, each terminal set having at least two electrical contacts. A controller determines an insertion condition if each of the terminal sets is shorted, and determines a non-insertion condition if only one terminal set is shorted, or if neither of the terminal sets is shorted.

Abstract: Embodiments relate to a method of decomposing a layout of a semiconductor device. The method may include generating a pattern layout including first patterns and second patterns, generating an interference map for the pattern layout, the interference map including optical interference information regarding the first and second patterns, and decomposing the pattern layout into a first decomposition pattern layout including the first patterns, and a second decomposition pattern layout including the second patterns, based on the interference map. In the interference map, an influence of constructive interference on the first patterns may be greater than an influence of constructive interference on the second patterns.

Abstract: A latency control circuit includes a clock delay configured to output a plurality of serial delay signals obtained by serially delaying an input clock signal with the same intervals, a deviation information generating unit configured to generate a deviation information on the basis of a delay value, which the clock signal undergoes in a chip, and latency information, a clock selector configured to output a plurality of clock selection signals based on the plurality of serial delay signals and the deviation information, a command signal processing unit configured to generate a read signal based on an input command signal, and output a variable delay duplication signal by variably delaying the read signal, and a latency shifter configured to output a latency signal by combining the plurality of clock selection signals with the variable delay duplication signal.

Abstract: A method of forming a line/space pattern includes forming a plurality of first pattern structures on a layer of hard mask material disposed on a substrate, forming a plurality of second pattern structures along sidewalls of the first pattern structures, removing the first pattern structures such that the second pattern structures stand alone on the layer of hard mask material, forming a first mask that exposes a location where a space of the line/space pattern to be formed is to have a width greater than the distance between adjacent ones of the second pattern structures, removing those of the second pattern structures which are exposed by the first mask such that others of the second pattern structures remain on the layer of hard mask material, forming a second mask that covers a location where a line of the line/space pattern to be formed is to have a width that is greater than the widths of the second pattern structures, forming a hard mask by etching the hard mask material layer using the second mask and

Abstract: An image signal modifying device includes a pixel, a memory which stores compressed information in which a three-dimensional (“3-D”) lookup table is coded, an image signal modifying unit which decodes the compressed information to generate a restored 3-D lookup table and generates a modified signal based on a first image signal of a first frame, a second image signal of a second frame, a third image signal of a third frame and the restored 3-D lookup table, and a data driver which converts the modified signal into the data voltage and supplies the data voltage to the pixel.

Abstract: A method of processing data including dividing, at a transmitter, data into 3-bit units, generating, at the transmitter, first and second clock embedded data signals and a third data signal, wherein a clock signal and first bits of the units are included in the first clock embedded data signal, the clock signal and second bits of the units are included in the second clock embedded data signal and third bits of the units are included in the third data signal, transmitting, from the transmitter to a receiver, the first and second clock embedded data signals and the third data signal, and restoring, at the receiver, the first and second bits and the clock signal from the first and second clock embedded data signals and the third bits from the third data signal.