Patents by Inventor In-Gwang Kim

In-Gwang Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250103464
    Abstract: A root cause analysis system according to an embodiment of the present disclosure may include: an Analysis tool calculator that operates in a microservice environment and calculates a corresponding analysis tool, which is a member of analyzing a root cause of target software, based on comparison software configured of corresponding independent modules, which are independent modules classified by function to correspond to the target software, which is software to be analyzed; and a Cause analyser that analyzes the root cause of an abnormal operation occurring in the target software using the corresponding analysis tool.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 27, 2025
    Applicant: OKESTRO CO., LTD.
    Inventors: Chang Hoon LEE, Min Jae SONG, Eun Soo KO, Young Gwang KIM, Min Jun KIM
  • Publication number: 20250106218
    Abstract: A calculation system that calculates a usage right for resources of a cloud server by a user using a cloud service according to an embodiment of the present disclosure may include: a reception module that generates analysis activity information, which is activity information generated while the user uses the cloud server, in order to determine the usage right; a right module that uses a predetermined analysis method based on the analysis activity information to calculate a corresponding right, which is the usage right corresponding to the analysis activity information and applicable only to a specific user; and a transmission module that transmits a recommendation right calculated utilizing the corresponding right through a predetermined path.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 27, 2025
    Applicant: OKESTRO CO., LTD.
    Inventors: A Ron JEONG, Sang Yong LEE, Do Hoon KIM, Young Gwang KIM, Min Jun KIM
  • Publication number: 20250098179
    Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits with MOSFET transistors. The CMOS layer may also include memory cells, e.g., SRAM cells. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. A logic circuit in the CMOS layer may control access to the memory cells. A memory layer may be bonded with the CMOS layer through a bonding layer that includes conductive structures coupled to a logic circuit in the CMOS layer or to bit lines or word lines in the memory layer. An additional conductive structure may be at the backside of a MOSFET transistor in the CMOS layer and coupled to a conductive structure in the bonding layer.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 20, 2025
    Inventors: Abhishek A. Sharma, Van H. Le, Fatih Hamzaoglu, Juan G. Alzate-Vinasco, Nikhil Jasvant Mehta, Vinaykumar Hadagali, Yu-Wen Huang, Honore Djieutedjeu, Tahir Ghani, Timothy Jen, Shailesh Kumar Madisetti, Jisoo Kim, Wilfred Gomes, Kamal Baloch, Vamsi Evani, Christopher Wiegand, James Pellegren, Sagar Suthram, Christopher M. Pelto, Gwang Soo Kim, Babita Dhayal, Prashant Majhi, Anand Iyer, Anand S. Murthy, Pushkar Sharad Ranade, Pooya Tadayon, Nitin A. Deshpande
  • Publication number: 20250065996
    Abstract: A method of calculating a collision risk of a ship according to an embodiment of the present disclosure may include: calculating an available velocity area based on maneuvering performance of a host ship; calculating a velocity obstacle area where there is a possibility of collision between an object and the host ship; and calculating a collision risk based on at least one of the available velocity area, the velocity obstacle area, and a preset weight.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 27, 2025
    Inventors: Kwang Sung KO, In Beom KIM, Jin Mo PARK, Hui Yong CHOI, Hu Jae CHOI, Su Rim KIM, Gwang Hyeok CHOI, Do Yeop LEE, Do Yeon JUNG, Jin Young OH, Je Hyun CHA, Ji Yoon PARK, Won Chul YOO
  • Publication number: 20250036245
    Abstract: An interface device includes an electronic device and an input device. The electronic device includes a display layer that includes a display area that includes a foldable area and non-foldable areas, a sensor layer that includes a plurality of detection electrodes, and a sensor driving unit that drives the sensor layer. The plurality of detection electrodes include a first pen sensing electrode and a second pen sensing electrode, and the sensor driving unit transmits to the first pen sensing electrode one of a first sensing signal that has a first driving frequency or a second sensing signal that has a second driving frequency that differs from the first driving frequency according to a position of the input device with respect to the display area.
    Type: Application
    Filed: July 9, 2024
    Publication date: January 30, 2025
    Inventors: MIYOUNG KIM, KYOWON KU, GWANG-BUM KO
  • Patent number: 12211803
    Abstract: A semiconductor device has a substrate and an electrical component disposed over a surface of the substrate. An antenna interposer is disposed over the substrate. A first encapsulant is deposited around the antenna interposer. The first encapsulant has a high dielectric constant. The antenna interposer has a conductive layer operating as an antenna and an insulating layer having a low dielectric constant less than the high dielectric constant of the first encapsulant. The antenna interposer is made from an antenna substrate having a plurality of antenna interposers. Bumps are formed over the antenna substrate and the antenna substrate is singulated to make the plurality of antenna interposers. A second encapsulant is deposited over the electrical component. The second encapsulant has a low dielectric constant less than the high dielectric constant of the first encapsulant. A shielding layer is disposed over the second encapsulant.
    Type: Grant
    Filed: December 20, 2023
    Date of Patent: January 28, 2025
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HunTeak Lee, Gwang Kim, Junho Ye, YouJoung Choi, MinKyung Kim, Yongwoo Lee, Namgu Kim
  • Patent number: 12190170
    Abstract: A virtual machine placement system for placing a plurality of virtual machines on a first physical server and a second physical server in order to efficiently operate a physical server in which the plurality of virtual machines are installed is disclosed. The physical server includes the first physical server and the second physical server, the virtual machine placement system contains a workload calculation module, a prediction module, a temperature prediction module, a schedule module, and a migration module, wherein the schedule module calculates a placement schedule considering predicted temperature of the physical server.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 7, 2025
    Assignee: OKESTRO CO., LTD.
    Inventors: Ho Yeong Yun, Hyun Suk Jang, Yoo Jong Lee, Young Gwang Kim, Min Jun Kim
  • Patent number: 12159156
    Abstract: A virtual machine placement system for placing a plurality of virtual machines on a first physical server and a second physical server in order to efficiently operate a physical server in which the plurality of virtual machines are installed is provided. The physical server includes the first physical server and the second physical server. The virtual machine placement system includes a workload calculation module; a prediction module; a temperature prediction module; a schedule module; and a migration module. The schedule module calculates a placement schedule considering a predicted temperature of the physical server.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: December 3, 2024
    Assignee: OKESTRO CO., LTD.
    Inventors: Ho Yeong Yun, Yoo Jong Lee, Chan Jae Lee, Young Gwang Kim, Min Jun Kim
  • Publication number: 20240296329
    Abstract: An apparatus for multi-label class classification based on a coarse-to-fine convolutional neural network includes: a processor; and a memory connected to the processor, in which the memory stores program instructions executed by the processor to generate a plurality of hierarchical structure based group labels for a plurality of classes to be classified by using a disjoint grouping method, predict classes which belong to the plurality of group labels, respectively among the plurality of classes by using a coarse-to-fine convolutional neural network including a main network and one or more subnetworks, complete learning of the coarse-to-fine convolutional network through the prediction, and classify one or more classes included in the image by receiving a feature map input from a last convolutional layer of the one or more subnetworks by the main network of the coarse-to-fine convolutional neural network of which learning is completed.
    Type: Application
    Filed: May 9, 2024
    Publication date: September 5, 2024
    Inventors: Joon Ki PAIK, Jin Ho PARK, Hee Gwang KIM, Min Woo SHIN
  • Patent number: 12079654
    Abstract: Provided is a virtual machine (VM) management method of simulating a change in deployment of VMs deployed on physical servers including a first physical server and a second physical server physically separated from the first physical server and scheduling deployment of VMs and predicting workload of VMs.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: September 3, 2024
    Assignee: OKESTRO CO., LTD.
    Inventors: Ho Yeong Yun, Young Gwang Kim, Min Jun Kim
  • Publication number: 20240290671
    Abstract: A semiconductor package comprises: a package substrate comprising: a first portion comprising a first conductive pattern extending therewithin having a first thickness; and a second portion comprising a second conductive pattern extending therewithin having a second thickness smaller than the first thickness; at least one electronic component mounted on the second portion and electrically coupled to the second conductive pattern; an encapsulant layer formed on the second portion of the package substrate and covering the at least one electronic component, wherein the encapsulant layer comprises a cavity region; a connector assembly formed within the cavity region of the encapsulant layer and electrically coupled to the second conductive pattern, wherein the connector assembly is exposed from the encapsulant layer to allow for electrical connection with an external device; and a partial shielding layer formed on at least regions other than the cavity region of the encapsulant layer.
    Type: Application
    Filed: February 21, 2024
    Publication date: August 29, 2024
    Inventors: Gwang KIM, HunTeak LEE
  • Publication number: 20240261828
    Abstract: A self-cleaning device and a method of operating the same for removing droplet, high viscosity liquid material or mixed material using heating, multi-voltage applying or vibration are disclosed. The self-cleaning device comprises a metal material layer disposed on a solid material layer and a hydrophobic layer disposed on the metal material layer. The metal material layer includes a view member formed of conductive material and a heating member disposed outside or inside the view member, heat is generated from the view member and the heating member when a power is applied to the view member and the heating member, the heat generated from the heating member is delivered to the view member, and droplet existed on a surface of the self-cleaning device is removed or a volume or surface tension of the droplet reduces by the heat generated from the view member and the heat delivered from the heating member.
    Type: Application
    Filed: April 19, 2024
    Publication date: August 8, 2024
    Inventors: Kang Yong LEE, Jeong Min LEE, Dae Young LEE, Dae Geun KIM, Young Gwang KIM, Jae Hun SHIN
  • Publication number: 20240153783
    Abstract: A semiconductor device has a substrate and a first component disposed over a first surface of the substrate. A connector is disposed over the first surface of the substrate. A first encapsulant is deposited over the first component while the connector remains outside of the first encapsulant. A shielding layer is formed over the first encapsulant while the connector remains outside of the shielding layer. A second component is disposed over a second surface of the substrate. A solder bump is disposed over the second surface of the substrate. A second encapsulant is deposited over the second surface of the substrate. An opening is formed through the second encapsulant to expose the solder bump. A solder ball is disposed in the opening. The solder ball and solder bump are reflowed to form a combined solder bump.
    Type: Application
    Filed: December 18, 2023
    Publication date: May 9, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: HunTeak Lee, Gwang Kim, Junho Ye
  • Publication number: 20240128201
    Abstract: A semiconductor device has a substrate and an electrical component disposed over a surface of the substrate. An antenna interposer is disposed over the substrate. A first encapsulant is deposited around the antenna interposer. The first encapsulant has a high dielectric constant. The antenna interposer has a conductive layer operating as an antenna and an insulating layer having a low dielectric constant less than the high dielectric constant of the first encapsulant. The antenna interposer is made from an antenna substrate having a plurality of antenna interposers. Bumps are formed over the antenna substrate and the antenna substrate is singulated to make the plurality of antenna interposers. A second encapsulant is deposited over the electrical component. The second encapsulant has a low dielectric constant less than the high dielectric constant of the first encapsulant. A shielding layer is disposed over the second encapsulant.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 18, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: HunTeak Lee, Gwang Kim, Junho Ye, YouJoung Choi, MinKyung Kim, Yongwoo Lee, Namgu Kim
  • Patent number: 11950383
    Abstract: A display apparatus according to a concept of the disclosure includes: a display panel configured to display an image in a front direction; a top chassis positioned in a front direction of the display panel; a bottom chassis positioned in a rear direction of the display panel; a rear cover covering a rear side of the bottom chassis; and a stand member being accommodatable in the rear cover and selectively coupled with a rear surface of the rear cover, wherein the rear cover includes an accommodating portion in which the stand member is accommodated and a coupling portion coupled with the stand member, and the stand member includes an inserting protrusion which is inserted into the accommodating portion and the coupling portion.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: April 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-Bong Kim, Dong Wook Kim, Ji-Gwang Kim, Tae-Hun Kim, Yong Gu Do, Jeong Woo Park, Gil Jae Lee, Sang Young Lee, Pil Kwon Jung, Su-An Choi
  • Patent number: D1020697
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: April 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeewon Kim, Ji-Gwang Kim, Sung-Il Bang, Junpyo Kim
  • Patent number: D1021834
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: April 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-Ho Kim, Seung-Ho Lee, Ji-Gwang Kim, Sang-Young Lee, Jin-Su Park
  • Patent number: D1035601
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: July 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaewook Yoo, Ji-Gwang Kim, Daehun Jung, Byungmin Woo
  • Patent number: D1041444
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: September 10, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Bang, Ji-Gwang Kim, Junpyo Kim, Jeewon Kim
  • Patent number: D1042378
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: September 17, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaewook Yoo, Ji-Gwang Kim, Daehun Jung, Byungmin Woo