Patents by Inventor In Hak HAN

In Hak HAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240346218
    Abstract: The technical idea of the present disclosure pertains to a simulation method and an integrated circuit simulation system for estimating power consumption of an integrated circuit. The method, according to this technical idea, involves determining a clock domain based on a clock flow in the integrated circuit, executing simulation for various modeling signals with different patterns in the targeted modeling clock domain, collecting an energy value consumed by each of the modeling signals based on a simulation result, and calculating the power consumption of the modeling clock domain based on at least one characteristic of the simulation clock.
    Type: Application
    Filed: November 30, 2023
    Publication date: October 17, 2024
    Inventors: In Hak HAN, Jonggyu KIM
  • Patent number: 11755097
    Abstract: Example embodiments relate to a method for modeling power consumption of an integrated circuit, the method may comprise, determining, by the processor, a hierarchy structure regarding a gating level according to a clock flow of a plurality of clock gating cells included in the integrated circuit, determining, by the processor, a first clock gating domain corresponding to a first clock gating cell and a second clock gating domain corresponding to a second clock gating cell located in a lower level of the hierarchy of the first clock gating cell based on the hierarchy structure, calculating, by the processor, power consumption of the second clock gating domain based on a first logic level of a first clock gating enable signal applied to the first clock gating cell, and modeling, by the processor, power consumption of the integrated circuit based on the power consumption of the second clock gating domain.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: September 12, 2023
    Assignee: Baum Design Systems Co., Ltd.
    Inventors: In Hak Han, Jin Hyeong Park
  • Publication number: 20230010159
    Abstract: Example embodiments relate to a method for modeling power consumption of an integrated circuit, the method may comprise, determining, by the processor, a hierarchy structure regarding a gating level according to a clock flow of a plurality of clock gating cells included in the integrated circuit, determining, by the processor, a first clock gating domain corresponding to a first clock gating cell and a second clock gating domain corresponding to a second clock gating cell located in a lower level of the hierarchy of the first clock gating cell based on the hierarchy structure, calculating, by the processor, power consumption of the second clock gating domain based on a first logic level of a first clock gating enable signal applied to the first clock gating cell, and modeling, by the processor, power consumption of the integrated circuit based on the power consumption of the second clock gating domain.
    Type: Application
    Filed: June 27, 2022
    Publication date: January 12, 2023
    Inventors: In Hak HAN, Jin Hyeong PARK
  • Patent number: 11475190
    Abstract: Example embodiments relate to a method for designing integrated circuit based on a computer program including at least one instruction performed by an integrated circuit design system including a processor, the method comprising mapping, by the processor, at least one netlist signal to at least one RTL signal, determining, by the processor, a target netlist signal among the at least one netlist signal, determining, by the processor, a target expression of the target netlist signal using the netlist signal mapped to the at least one RTL signal based on at least a part of the netlist circuit, simulating, by the processor, on the at least one RTL signal, calculating, by the processor, signal simulation predicting information for the target netlist signal using the target expression and generating, by the processor, a design model by designing an integrated circuit using the signal simulation predicting information.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: October 18, 2022
    Assignee: Baum Design Systems Co., Ltd.
    Inventors: In Hak Han, Joon Hwan Yi
  • Publication number: 20220156445
    Abstract: The present disclosure relates to a method of predicting power consumption of an integrated circuit. The method includes receiving a gate-level netlist of the integrated circuit, receiving a plurality of libraries defining operation of at least one cell included in the netlist, receiving signal switching information in the netlist, receiving a target corner including a target operating voltage (VDDtarg) and a target temperature (Ttarg), and estimating switching power at the target corner of the integrated circuit on the basis of the netlist, the signal switching information, and the target operating voltage (VDDtarg).
    Type: Application
    Filed: September 10, 2021
    Publication date: May 19, 2022
    Inventor: In Hak HAN
  • Patent number: 10878155
    Abstract: A computer-implemented method of estimating leakage power of a circuit design may include: obtaining waveform data by performing a functional simulation on a circuit design according to reference input signals; obtaining leakage power data by calculating power consumption of the circuit design according to the waveform data; generating a leakage power model of the circuit design based on the waveform data and the leakage power data; and estimating leakage power of the circuit design by performing a functional simulation on the circuit design according to test input signals on a basis of the leakage power model.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: December 29, 2020
    Assignee: BAUM CO., LTD.
    Inventors: Jong Gyu Kim, In Hak Han
  • Publication number: 20200151296
    Abstract: A computer-implemented method of estimating leakage power of a circuit design may include: obtaining waveform data by performing a functional simulation on a circuit design according to reference input signals; obtaining leakage power data by calculating power consumption of the circuit design according to the waveform data; generating a leakage power model of the circuit design based on the waveform data and the leakage power data; and estimating leakage power of the circuit design by performing a functional simulation on the circuit design according to test input signals on a basis of the leakage power model.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 14, 2020
    Inventors: Jong Gyu KIM, In Hak HAN
  • Publication number: 20190332934
    Abstract: Provided is an apparatus for manufacturing an integrated circuit including a clock network, the apparatus including a preprocessor configured to obtain at least one input parameter and an input netlist including the clock network; a neural network interface configured to provide the input netlist and the at least one input parameter to at least one artificial neural network (ANN) that has been trained based on a plurality of netlists and a plurality of parameters, and receive, from the at least one ANN, at least one output parameter that defines the clock network, wherein the plurality of netlists and the plurality of parameters correspond to a plurality of sample clock networks; and a power calculator configured to calculate power consumption of the clock network, based on the at least one output parameter.
    Type: Application
    Filed: September 4, 2018
    Publication date: October 31, 2019
    Inventor: In Hak HAN