Abstract: An apparatus and method of measuring pattern uniformity, and a method of manufacturing a mask by using the measurement method are provided. The measurement apparatus includes a light source configured to generate and output light, a stage configured to support a measurement target, an optical system configured to transfer the light, output from the light source, to the measurement target supported on the stage, and a first detector configured to detect light reflected and diffracted by the measurement target, or diffracted by passing through the measurement target, wherein the first detector is configured to detect a pupil image of a pupil plane and to measure pattern uniformity of an array area of the measurement target on the basis of intensity of at least one of zero-order light and 1st-order light of the pupil image.

Abstract: A particle beam system includes: a particle source to generate a beam of charged particles; a first multi-lens array including a first multiplicity of individually adjustable and focusing particle lenses so that at least some of the particles pass through openings in the multi-lens array in the form of a plurality of individual particle beams; a second multi-aperture plate including a multiplicity of second openings downstream of the first multi-lens array so that some of the particles which pass the first multi-lens array impinge on the second multi-aperture plate and some of the particles which pass the first multi-lens array pass through the openings in the second multi-aperture plate; and a controller configured to supply an individually adjustable voltage to the particle lenses of the first multi-lens array and thus individually adjust the focusing of the associated particle lens for each individual particle beam.

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one pillar extends through the stack structure. The at least one pillar includes at least one insulative material and a channel structure horizontally surrounding the at least one insulative material. The at least one channel structure comprises sub-regions of semiconductor material. At least one of the sub-regions exhibits a different microstructure than at least one other of the sub-regions. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

Abstract: Provided are an optical modulating device and a system including the optical modulating device. The optical modulating device includes a substrate, and a phase modulator formed on the substrate and including a Fabry-Perot cavity. The Fabry-Perot cavity of the phase modulator includes a first reflective layer, a second reflective layer, and a tunable core formed between the first reflective layer and the second reflective layer, wherein the tunable core is formed of a semiconductor material and is configured to modulate a phase of light corresponding to modulation of a refractive index of the tunable core according to electrical control.

Abstract: A display device includes: a substrate; a reinforcement layer on the substrate; and a display layer comprising a barrier layer on the reinforcement layer, wherein a number of hydrogen atoms of the reinforcement layer per unit volume is less than a number of hydrogen atoms of the barrier layer per unit volume.

Abstract: The present specification relates to a heterocyclic compound represented by Chemical Formula 1, and an organic light emitting device comprising the same.

Abstract: A semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells include at least one second transistor, where the control circuits control the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least one of the memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.

Abstract: A vehicle, system and method of detecting an internal short in a battery pack of the vehicle. The system includes a plurality of sensors and a processor. The plurality of sensors obtains states of charge at battery cells of the battery pack. The processor discharges the battery pack to identify a first set of the battery cells based on the states of charge of the battery cells, charges the battery pack to identify a second set of the battery cells based on the states of charge of the battery cells, and generates an alarm when an intersection of the first set and the second set is non-empty.

Abstract: An interactive textile configured to provide a haptic feedback in response to an activating signal. The interactive textile includes a fabric; an electroactive layer disposed on the fabric, the electroactive layer having a first main side and a second main side; a first electrode disposed between the first main side of the electroactive layer and the fabric; and a second electrode disposed on the second main side of the electroactive layer. A method of forming an interactive textile configured to provide a haptic feedback in response to an activating signal is also provided.

Abstract: A block of data intended for a set of receiving computer systems comprising a first system and a second system is divided into a set of equal-size portions. A first portion of the set of portions is transmitted from a first file server storing the block of data to the first system. The first portion is relayed from the first file server to a second file server concurrently with the transmitting. The first portion of the set of portions is transmitted from the second file server to the second system.

Abstract: A method of operating a beamline ion implanter may include performing, in an ion implanter, a first implant procedure to implant a dopant of a first polarity into a given semiconductor substrate, and generating an estimated implant dose of the dopant of the first polarity based upon a set of filtered information, generated by the first implant procedure. The method may also include calculating an actual implant dose of the dopant of the first polarity using a predictive model based upon the estimated implant dose, and performing, in the ion implanter, an adjusted second implant procedure to implant a dopant of a second polarity into a select semiconductor substrate, based upon the actual implant dose.

Abstract: A resistive memory device includes: conductive layers and interlayer insulating layers, which are alternatively stacked; a vertical hole vertically penetrating the conductive layers and the interlayer insulating layers; a gate insulating layer disposed over an inner wall of the vertical hole; a charge trap layer disposed over an inner wall of the gate insulating layer; a channel layer disposed over an inner wall of the charge trap layer; and a variable resistance layer disposed over an inner wall of the channel layer.

Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (?m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 ?m or less.

Abstract: The present disclosure relates to a layout structure forming method of a sense amplifier and a layout structure of a sense amplifier. The method includes: providing a first active region layout structure layer, the first metal contact pattern layer includes a first metal contact pattern and a second metal contact pattern that are located on two opposite sides of the first pattern region; the first conductive wire pattern layer includes a first conductive wire pattern covering the first metal contact pattern and the second metal contact pattern; and the first connection hole pattern layer includes a plurality of connection hole designs, and the connection hole designs are connected to form a connection structure connected to the first metal contact pattern layer.

Abstract: Disclosed herein are an apparatus and method for preventing a security threat to a virtual machine. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program is configured such that a hypervisor for virtualization in a host kernel executes a virtualization instruction corresponding to the service requested by a virtual machine of a host application and such that a hypervisor for monitoring interrupts the virtualization instruction in response to a security threat event occurring in the monitoring area of the hypervisor for virtualization and controls the process and thread of the host kernel. The hypervisor for monitoring is located in an area separate from the area in which the hypervisor for virtualization is located in the host kernel.

Abstract: An electrode assembly includes a plurality of electrodes arranged in a stack along a stacking axis with a respective separator portion of an elongated separator sheet positioned between and winding around each of the electrodes in the stack along a serpentine path. The plurality of electrodes include a top electrode positioned at a top of the stack along the stacking axis, and the plurality of electrodes include a bottom electrode positioned at a bottom of the stack. The separator portions in the stack include a top separator portion abutting the top electrode and a bottom separator portion abutting the bottom electrode. The top separator portion and the bottom separator portion each have a value of air permeability from 80 sec/100 ml to 120 sec/100 ml per square inch of the respective separator portion at a pressure of 0.05 MPa and at room temperature.

Abstract: The present invention relates to high doses of macitentan, i.e. propylsulfamic acid [5-(4-bromo-phenyl)-6-[2-(5-bromo-pyrimidin-2-yloxy)-ethoxy]-pyrimidin-4-yl]-amide or pharmaceutically acceptable salts, solvates, hydrates or morphological forms thereof, or of aprocitentan, for use in the treatment and/or prevention of pulmonary arterial hypertension (PAH). Moreover, the present invention relates to the use of high doses of macitentan, or of aprocitentan, for the manufacture of a medicament for the treatment and/or prevention of PAH, as well as to a method for the treatment and/or prevention of PAH comprising high doses of macitentan or of aprocitentan. Further, the present invention relates to a dosage regimen for the treatment and/or prevention of PAH as well as to a combination of macitentan, or of aprocitentan, with one or more phosphodiesterase type 5 (PDE5) inhibitors, prostacyclin analogues, prostacyclin receptor agonists or soluble guanylate cyclase stimulators.

Abstract: A camera module is provided. The camera module includes a carrier; a lens holder accommodated in the carrier; an optical image stabilization (OIS) cover coupled to the carrier and disposed on the lens holder; and first buffer members coupled to the OIS cover, wherein a distance between the lens holder and the first buffer member is less than a distance between the lens holder and the OIS cover.

Abstract: A partitioning method comprises determining whether a current block of a picture is a boundary block and whether the size of the current block is larger than a minimum allowed quadtree leaf node size; and if the current block is the boundary block and the size of the current block is not larger than the minimum allowed quadtree leaf node size (MinQTSize), applying forced binary tree (BT) partitioning to the current block. A method comprises making a determination that a current block of a picture is a boundary block and that a size of the current block is less than or equal to a minimum allowed quadtree (QT) leaf node size (MinQTSize); and applying, in response to the determination, forced binary tree (BT) partitioning to the current block.

Abstract: A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.