Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In video encoding and decoding, multiple partition blocks are generated by splitting a target block. A prediction mode is derived for at least a part of the multiple partition blocks, among the multiple partition blocks, and prediction is performed on the multiple partition blocks based on the derived prediction mode. When prediction is performed on the partition blocks, information related to the target block may be used, and information related to an additional partition block, which is predicted prior to the partition block, may be used.

Abstract: An exemplary semiconductor device can comprise (a) a substrate comprising a substrate dielectric structure between the substrate top side and the substrate bottom side, conductive pads at the substrate bottom side, and a substrate cavity through the substrate dielectric structure, (b) a base electronic component comprising inner short bumps; outer short bumps bounding a perimeter around the inner short bumps, and tall bumps between the outer short bumps and an edge of the base component top side, and (c) a mounted electronic component coupled to the inner short bumps of the base electronic component. The tall bumps of the base component can be coupled to the conductive pads of the substrate. The mounted electronic component can be located in the substrate cavity. The substrate bottom side can cover at least a portion of the outer short bumps of the base electronic component. Other examples and related methods are disclosed herein.

Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In video encoding and decoding, multiple partition blocks are generated by splitting a target block. A prediction mode is derived for at least a part of the multiple partition blocks, among the multiple partition blocks, and prediction is performed on the multiple partition blocks based on the derived prediction mode. When prediction is performed on the partition blocks, information related to the target block may be used, and information related to an additional partition block, which is predicted prior to the partition block, may be used.

Abstract: An exemplary semiconductor device can comprise (a) a substrate comprising a substrate dielectric structure between the substrate top side and the substrate bottom side, conductive pads at the substrate bottom side, and a substrate cavity through the substrate dielectric structure, (b) a base electronic component comprising inner short bumps; outer short bumps bounding a perimeter around the inner short bumps, and tall bumps between the outer short bumps and an edge of the base component top side, and (c) a mounted electronic component coupled to the inner short bumps of the base electronic component. The tall bumps of the base component can be coupled to the conductive pads of the substrate. The mounted electronic component can be located in the substrate cavity. The substrate bottom side can cover at least a portion of the outer short bumps of the base electronic component. Other examples and related methods are disclosed herein.

Abstract: A memory system includes: a memory device including a plurality of pages each including a plurality of L-level cells, K planes each including the plurality of pages, and N memory dies each including the K planes; and a controller suitable for dividing logical addresses corresponding to write data, into a plurality of divided logical groups by grouping the logical addresses by a preset number, when performing a program operation of transferring the write data to the memory device to store, and mapping each of the plurality of divided logical groups to a reference logical unit in a first order of bits of the L-level cell, a second order of the N memory dies, and a third order of the K planes, according to a size of the write data, in order to decide an order in which the write data are to be transferred to the memory device.

Abstract: A controller controls an operation of a semiconductor memory device including a reference storage area and a normal storage area. The controller includes a power supply sensor, a command generator, and a refresh count manager. The power supply sensor generates a power-on signal indicating that a memory system including the controller is powered-on. The command generator generates a read command for reading reference data stored in the reference storage area in response to the power-on signal and transfer the read command to the semiconductor memory device. The refresh count manager analyzes the read reference data received from the semiconductor memory device and determines whether a threshold voltage distribution of memory cells included in the reference storage area is changed. The command generator controls the semiconductor memory device to perform a refresh operation on the reference data stored based on a result of the determination of the refresh count manager.

Abstract: A memory system may perform a first read retry operation using at least one read bias of multiple read biases in a priority read bias group, among a plurality of read biases; and perform, according to a result of the first read retry operation, a second read retry operation using one or more remaining read biases, not in the priority read bias group, in the read retry table. At this time, the read biases in the priority read bias group may be selected prior to the remaining read biases when performing the read retry operation on the target memory area. As a result, the memory system is able to minimize degradation of reading performance due to the read retry operation and reduce the number of unnecessary reads when performing the read retry operation.

Abstract: An exemplary semiconductor device can comprise (a) a substrate comprising a substrate dielectric structure between the substrate top side and the substrate bottom side, conductive pads at the substrate bottom side, and a substrate cavity through the substrate dielectric structure, (b) a base electronic component comprising inner short bumps; outer short bumps bounding a perimeter around the inner short bumps, and tall bumps between the outer short bumps and an edge of the base component top side, and (c) a mounted electronic component coupled to the inner short bumps of the base electronic component. The tall bumps of the base component can be coupled to the conductive pads of the substrate. The mounted electronic component can be located in the substrate cavity. The substrate bottom side can cover at least a portion of the outer short bumps of the base electronic component. Other examples and related methods are disclosed herein.

Abstract: An exemplary semiconductor device can comprise (a) a substrate comprising a substrate dielectric structure between the substrate top side and the substrate bottom side, conductive pads at the substrate bottom side, and a substrate cavity through the substrate dielectric structure, (b) a base electronic component comprising inner short bumps; outer short bumps bounding a perimeter around the inner short bumps, and tall bumps between the outer short bumps and an edge of the base component top side, and (c) a mounted electronic component coupled to the inner short bumps of the base electronic component. The tall bumps of the base component can be coupled to the conductive pads of the substrate. The mounted electronic component can be located in the substrate cavity. The substrate bottom side can cover at least a portion of the outer short bumps of the base electronic component. Other examples and related methods are disclosed herein.

Abstract: A memory system may perform a first read retry operation using at least one read bias of multiple read biases in a priority read bias group, among a plurality of read biases; and perform, according to a result of the first read retry operation, a second read retry operation using one or more remaining read biases, not in the priority read bias group, in the read retry table. At this time, the read biases in the priority read bias group may be selected prior to the remaining read biases when performing the read retry operation on the target memory area. As a result, the memory system is able to minimize degradation of reading performance due to the read retry operation and reduce the number of unnecessary reads when performing the read retry operation.

Abstract: Provided herein may be a controller, a memory system including the controller, and a method of operating the memory system. The controller may include a processor configured to control a read operation of a memory device in response to a read command received from a host and an error correction circuit configured to perform an error correction operation on read data received from the memory device during the read operation. The processor may determine deterioration characteristics of the memory device during the read operation, and control the memory device to select and perform any one of a re-program operation and a reclaim operation on memory cells on which the read operation has been performed.

Abstract: An exemplary semiconductor device can comprise (a) a substrate comprising a substrate dielectric structure between the substrate top side and the substrate bottom side, conductive pads at the substrate bottom side, and a substrate cavity through the substrate dielectric structure, (b) a base electronic component comprising inner short bumps; outer short bumps bounding a perimeter around the inner short bumps, and tall bumps between the outer short bumps and an edge of the base component top side, and (c) a mounted electronic component coupled to the inner short bumps of the base electronic component. The tall bumps of the base component can be coupled to the conductive pads of the substrate. The mounted electronic component can be located in the substrate cavity. The substrate bottom side can cover at least a portion of the outer short bumps of the base electronic component. Other examples and related methods are disclosed herein.

Abstract: Provided herein may be a controller, a memory system including the controller, and a method of operating the memory system. The controller may include a processor configured to control a read operation of a memory device in response to a read command received from a host and an error correction circuit configured to perform an error correction operation on read data received from the memory device during the read operation. The processor may determine deterioration characteristics of the memory device during the read operation, and control the memory device to select is and perform any one of a re-program operation and a reclaim operation on memory cells on which the read operation has been performed.

Abstract: Provided are a method for predicting a mortality risk or a sepsis risk, implemented by a processor, to predict an emergency situation, and a device using the same. The method for predicting a mortality risk or a sepsis risk includes: receiving biological signal data for a subject from a biological signal prediction device; generating a risk sequence for the subject based on the biological signal data, by using a risk sequence generation model configured to generate a risk sequence based on the biological signal data; and predicting a risk for the subject based on the risk sequence.