Abstract: Disclosed are peptides having SEQ ID NOs: 1 to 32 that can stimulate superoxide generation in human monocytes. Superoxide is the most important armory on the primary defense line of monocytes against invading pathogens, and the identification of new stimuli and the characterization of the regulatory mechanism of superoxide generation are of paramount importance.

Abstract: A method and a device for locally heating a semiconductor wafer having a first region of a first impurity and a second region of a second impurity having a diffusion rate different from that of the first impurity. A field oxide layer, a P well and an N well, gate oxide layers, gate electrodes, an N-type region and a P-type region are formed in sequence on or in a silicon wafer. The wafer is placed into a chamber. Then, a mask, which has a pattern for blocking the radiation from the heat source to the N well of the wafer, is positioned between the heat source and the wafer. The heat source emits radiation for heating the wafer, thereby the donor-type dopant atoms in the N-type region are diffused with a diffusion depth of d2 to form an electrically active region, but the acceptor-type dopant atoms in the P-type region are not diffused. After this step, a mask, which has a pattern for blocking the radiation from the heat source to the P well of the wafer, is positioned between the heat source and the wafer.

Abstract: An improved call distribution processing method for a called line number computation in a premium-rate service of Intelligent Network is provided. The method is capable of routing to various called numbers designated in accordance with a calling area, performing a call distribution in accordance with the capacity of a called party number, and routing to a called number since this method does not degrade call processing performance of the system. Since a system load is less, the occurrence frequency per each digit when digits from one to a hundred is performed N-times evenly occurs, and the values which was generated in the function of the random numbers does not occur in the identical pattern.

Abstract: A method of processing information charge discount rates for service subscribers in a premium-rate service. Information charge discount rate data for each service subscriber is registered and a service subscriber number and a calling number are received from Service Switching Point. The received service subscriber number is designated as an index value of a main table in a service subscriber database and the main table is then retrieved to check whether data corresponding to the designated index value are present in the main table. If the data corresponding to the designated index value are present, a service feature classification data field in the main table is retrieved to check whether the service subscriber has subscribed to a flexible charging-by-day/time service.

Abstract: An interconnection structure of a semiconductor device for electrically connecting a thin conductive layer and a metallization and the fabrication method thereof are disclosed. The interconnection structure includes a semiconductor substrate, an insulating layer coated on the substrate, a thick conductive layer formed on a certain portion of the insulating layer, a first interlaid insulating layer covering the thick conductive layer, a first contact hole formed within the first interlaid insulating layer on the thick conductive layer, a thin conductive layer consisting of vertical structure formed in the first contact hole and horizontal structure formed on the first interlaid insulating layer, a second interlaid insulating layer covering the thin conductive layer, a second contact hole formed within said first and second interlaid insulating layers and crossing the first contact hole, and a metallization filling the second contact hole and formed on the second interlaid insulating layer.

Abstract: An interconnection structure of a semiconductor device for electrically connecting a thin conductive layer and a metallization and the fabrication method thereof are disclosed. The interconnection structure includes a semiconductor substrate, an insulating layer coated on the substrate, a thick conductive layer formed on a certain portion of the insulating layer, a first interlaid insulating layer covering the thick conductive layer, a first contact hole formed within the first interlaid insulating layer on the thick conductive layer, a thin conductive layer consisting of vertical structure formed in the first contact hole and horizontal structure formed on the first interlaid insulating layer, a second interlaid insulating layer covering the thin conductive layer, a second contact hole formed within said first and second interlaid insulating layers and crossing the first contact hole, and a metallization filling the second contact hole and formed on the second interlaid insulating layer.

Abstract: Disclosed is a method for fabricating a MOS transistor of the GOLD structure that allows self-aligning contact process and more precise control of low-concentration diffusion regions. The method characteristically includes the steps of: forming an oxide layer(55) over the conductive electrode(53a,54a,58a), the thickness of the oxide layer being sufficiently greater than the gate oxide layer, and depositing an insulating interlayer(61) over the semiconductor substrate after forming source and drain regions, the insulating interlayer being directionally etched through a photoresist pattern, so as to form a contact hole having a width extended up to a partial portion of the conductive electrode. The effective channel widths of the low-concentration diffusion regions may be precisely controlled only by adjusting the thickness of polysilicon (or refractory metal or silicide thereof) layer selectively deposited on the side walls of the conductive electrode.

Abstract: There is disclosed a stacked capacitor with high capacity which ensures structural stability in a DRAM cell and a method for manufacturing the same. The stacked-capacitor is of a hollow (or cylindrical) capacitor where both ends of several polysilicon layers which form a storage electrode are connected with each other. In construction, this inventive stacked-capacitor includes: a first polysilicon layer coupled to the source region so as to extend in parallel with surface of the substrate over the left and right sides of the source region; a bridge polysilicon layer, extending in the upward direction of the substrate from both ends of the first polysilicon layer; a dielectric film formed so as to contact with the surfaces of the bridge polysilicon layer, first polysilicon layer, second polysilicon layer; and a third polysilicon layer formed so as to contact with the surface of the dielectric film.

Abstract: There is disclosed a stacked capacitor comprising a fin-shaped storage electrode of multiple polysilicon layers with supporting layers therebetween so as to compensate for the structural weakness of the fin-shaped storage electrode.

Abstract: A stacked capacitor of the fin-like structure is provided wherein the plurality of polysilicon layers constituting the storage electrode are connected with each other in the sawtooth-like manner to overcome the structural instability of the fin-like structure. The polysilicon layers constituting the storage electrode are extended overlaying each other, so that the capacity of the capacitor in a highly integrated DRAM may be increased without increasing the area occupied by the capacitor.

Abstract: There is disclosed a stacked capacitor with high capacity which ensures structural stability in a DRAM cell and a method for manufacturing the same. The stacked-capacitor is of a hollow (or cylindrical) capacitor where both ends of several polysilicon layers which form a storage electrode are connected with each other. In construction, this inventive stacked-capacitor includes: a first polysilicon layer coupled to the source region so as to extend in parallel with surface of the substrate over the left and right sides of the source region; a bridge polysilicon layer, extending in the upward direction of the substrate from both ends of the first polysilicon layer; a dielectric film formed so as to contact with the surfaces of the bridge polysilicon layer, first polysilicon layer, second polysilicon layer; and a third polysilicon layer formed so as to contact with the surface of the dielectric film.

Abstract: Method for manufacturing polycrystalline silicon having high resistance, having a first step for depositing a polycrystalline silicon layer for a resistor area over a silicon semiconductor substrate; a second step for growing a first thermal oxide layer having a first specified depth over the polycrystalline silicon layer, ion-implanting with the nitrogen thereon, and growing a second thermal oxide layer having a second specified depth on the ion-implanted layer; a third step for forming a resistor pattern of the polycrystalline silicon with a photo etching method; and a fourth step for ion-implanting impurities in order to decrease the resistance of the polycrystalline silicon as contact regions to be used in resistance contacts with a fixed semiconductor region on the substrate.