Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.

Abstract: A memory device and method of making the same, the memory device including bit lines disposed on a substrate; memory cells disposed on the bit lines; a first dielectric layer disposed on the substrate, surrounding the bit lines and the memory cells; a second dielectric layer disposed on the first dielectric layer; thin film transistors (TFTs) embedded in the second dielectric layer and configured to selectively provide electric power to corresponding memory cells, the TFTs comprising drain lines disposed on the memory cells, source lines disposed on the first dielectric layer, and selector layers electrically connected to the source lines and the drain lines; and word lines disposed on the second dielectric layer and electrically connected to the TFTs.

Abstract: Methods of scaling the thickness of the interfacial layer in electronic devices, such as NMOS transistors and PMOS transistors are described. Some embodiments provide a metal film or a metal nitride film that reduces the thickness of the interfacial layer by scavenging unbound oxygen from the interfacial layer (e.g., silicon oxide (SiOx)) and the high-? dielectric layer (e.g., hafnium oxide (HfOx)). Some embodiments advantageously include annealing the semiconductor substrate to promote or accelerate the scavenging.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are disclosed. The semiconductor structure includes a dielectric layer and a transistor. The transistor is at least partially disposed in the dielectric layer. The transistor includes a gate electrode, a gate dielectric layer, a source electrode, a drain electrode and a semiconductor layer. The gate dielectric layer is disposed over the gate electrode. The source electrode and the drain electrode are disposed over the gate dielectric layer and contact the gate dielectric layer. The semiconductor layer is disposed over the gate dielectric layer.

Abstract: An image compensation circuit for an image sensor includes a gain amplifier, a compensation control circuit, a memory and a digital-to-analog converter (DAC). The gain amplifier is used for receiving a plurality of image signals from the image sensor and amplifying the plurality of image signals. The compensation control circuit is used for generating a plurality of compensation values for the plurality of image signals. The memory, coupled to the compensation control circuit, is used for storing the plurality of compensation values. The DAC, coupled to the memory and the gain amplifier, is used for converting the plurality of compensation values into a plurality of compensation voltages, respectively, to compensate the plurality of image signals with the plurality of compensation voltages.

Abstract: The present application provides a method for manufacturing a memory device having word lines with improved resistance, and a manufacturing method of the memory device. The method includes providing a semiconductor substrate defined with a peripheral region and an array region at least partially surrounded by the peripheral region; forming a first recess extending into the semiconductor substrate and disposed in the array region; and forming a word line disposed within the first recess. The formation of the word line includes disposing an insulating layer conformal to the first recess, and forming a conductive member surrounded by the insulating layer and having a second recess extending into the conductive member and toward the semiconductor substrate.

Abstract: Local execution of smart device mesh automations with cloud-based failover is described herein. Embodiments operate in context of network-connected devices in a smart device mesh with a local automation system, where all devices communicate with cloud-based automation, and at least some also communicate with local automation. A determination is made whether to claim each automation routine for local automation, or to automatically execute the automation by the cloud when triggered. Triggered locally claimed automation routines cause attempted default execution locally by local automation with automatic failover execution by the cloud-based automation. Some embodiments further involve electing an executor device as part of claiming an automation routine and/or monitoring execution of automation routines to determine when to automatically de-claim locally claimed automation routines with poor local execution success rates.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are disclosed. The semiconductor structure includes a dielectric layer and a transistor. The transistor is at least partially disposed in the dielectric layer. The transistor includes a gate electrode, a gate dielectric layer, a source electrode, a drain electrode and a semiconductor layer. The gate dielectric layer is disposed over the gate electrode. The source electrode and the drain electrode are disposed over the gate dielectric layer and contact the gate dielectric layer. The semiconductor layer is disposed over the gate dielectric layer.

Abstract: A memory device and method of making the same, the memory device including bit lines disposed on a substrate; memory cells disposed on the bit lines; a first dielectric layer disposed on the substrate, surrounding the bit lines and the memory cells; a second dielectric layer disposed on the first dielectric layer; thin film transistors (TFTs) embedded in the second dielectric layer and configured to selectively provide electric power to corresponding memory cells, the TFTs comprising drain lines disposed on the memory cells, source lines disposed on the first dielectric layer, and selector layers electrically connected to the source lines and the drain lines; and word lines disposed on the second dielectric layer and electrically connected to the TFTs.

Abstract: A memory structure includes: first and second word lines; a high-k dielectric layer disposed on the first and second word lines; a channel layer disposed on the high-k dielectric layer and comprising a semiconductor material; first and second source electrodes electrically contacting the channel layer; a first drain electrode disposed on the channel layer between the first and second source electrodes; a memory cell electrically connected to the first drain electrode; and a bit line electrically connected to the memory cell.

Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.

Abstract: An object of the present invention is to provide a material for organic EL elements, the material being excellent in hole injecting/transporting performance, electron-blocking capability, stability in the form of a thin film, and durability. Another object of the present invention is to provide an organic EL element having high efficiency, a low driving voltage, and a long lifespan, by combining the aforementioned material with various materials for organic EL elements, the materials being excellent in hole/electron injecting/transporting performance, electron-blocking capability, stability in the form of a thin film, and durability, such that the properties of the individual materials can be effectively exhibited.

Abstract: A method and an apparatus for allocating a flexible transmission slot in a wireless local area network (LAN) system are disclosed. A flexible transmission slot allocation method of an access point (AP) in a wireless local area network (WLAN) system according to an exemplary embodiment includes transmitting a beacon including a traffic indication map (TIM) bit to a station, receiving a power save poll (PS-Poll) from the station in a slot implicitly allocated by the TIM bit, and transmitting an acknowledgement (ACK) including transmission slot allocation information on downlink data to the station.

Abstract: An adjustable pneumatic-hydraulic pressure unit for stroke control including a cylinder and an actuating tube, an oil seal valve seat, a piston valve seat, and a plurality of pistons to form a plurality of oil chambers and a plurality of oil passages; whereby a piston is used to close to block or to open to conduct the oil passages, causing the oil-gas filled passages to form an internal pressure, which controls the actuating tube to be contracted downward or restored upward relative to the cylinder, so that the total exposed stroke of the actuating tube can be adjusted, and forms the pneumatic-hydraulic pressure unit with the function of stroke memory to cater the needs for riding and storing bicycles.

Abstract: A device for adjusting a seat height includes a fixation seat, an outer tube, an inner tube received in the outer tube, a cylinder housed in the inner tube, and a piston rod accommodated in the cylinder and combined with the inner tube. The fixation seat is attached to a bicycle seat. The outer tube is adapted to be connected with a bicycle frame. The piston rod can be displaced relative to the cylinder, so that the inner tube is driven by the piston rod to move relative to the outer tube within a displacement stroke, so as to adjust the height of the bicycle seat. In addition, the inner tube can be displaced relative to the piston rod by the rotation of the piston rod, so that the rider can adjust the bicycle seat height according to his own height or specific needs.

Abstract: A semiconductor package includes a first semiconductor chip that has a mount region and an overhang region, a substrate disposed on a bottom surface at the mount region of the first semiconductor chip, and a molding layer disposed on the substrate. The molding layer includes a first molding pattern disposed on a bottom surface at the overhang region of the first semiconductor chip and covering a sidewall of the substrate, and a second molding pattern on the first molding pattern and covering a sidewall of the first semiconductor chip.

Abstract: A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; an active layer disposed above the gate electrode; source/drain electrodes disposed above the gate electrode and separated by the active layer; and at least two dielectric layers disposed between the gate electrode and the source/drain electrodes.

Abstract: A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.

Abstract: A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; a gate dielectric layer disposed over the gate electrode; source/drain electrodes disposed above the gate electrode; and an active layer disposed above the gate electrode. A protection layer is disposed between the TFT and the MRAM cell and electrically connects the MRAM cell to the TFT.

Abstract: A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.