Patents by Inventor In Kwon Yang
In Kwon Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7906096Abstract: The present invention provides a chiral inorganic-organic composite porous material in which cationic chiral organic molecules are present as charge-balancing cations in a porous material containing charge-balancing cations, as well as a method for preparing the same by an ion exchange process. The chiral inorganic-organic composite porous material according to the present invention is excellent in stability, selectivity and durability, and thus, will be useful as a chiral-selective catalyst or a material of separating an isomeric mixture.Type: GrantFiled: January 7, 2005Date of Patent: March 15, 2011Assignee: ChiroliteInventors: Dong Han Bae, Chang Ick Lee, Seung Kwon Yang, Kyoung Tai No, Suk Kyu Chang, Byung Hee Seo, Jung Sup Kim, Jong Won Kim, Mee Kyung Song
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Patent number: 7611946Abstract: A method of fabricating a non-volatile memory device prevents the threshold voltage of a program-inhibited cell from rising by preventing hot carriers, generated in a semiconductor substrate near a select line, from being injected into a floating gate of the program-inhibited cell. The program-inhibited cell shares a word line adjacent to the select line such that a trench is formed in the semiconductor substrate between the select line and the adjacent word line to increase a distance between the select line and the word line.Type: GrantFiled: June 27, 2008Date of Patent: November 3, 2009Assignee: Hynix Semiconductor Inc.Inventor: In Kwon Yang
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Publication number: 20090098700Abstract: A method of fabricating a non-volatile memory device prevents the threshold voltage of a program-inhibited cell from rising by preventing hot carriers, generated in a semiconductor substrate near a select line, from being injected into a floating gate of the program-inhibited cell. The program-inhibited cell shares a word line adjacent to the select line such that a trench is formed in the semiconductor substrate between the select line and the adjacent word line to increase a distance between the select line and the word line.Type: ApplicationFiled: June 27, 2008Publication date: April 16, 2009Applicant: Hynix Semiconductor Inc.Inventor: In Kwon Yang
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Publication number: 20090018334Abstract: The present invention provides a chiral inorganic-organic composite porous material in which cationic chiral organic molecules are present as charge-balancing cations in a porous material containing charge-balancing cations, as well as a method for preparing the same by an ion exchange process. The chiral inorganic-organic composite porous material according to the present invention is excellent in stability, selectivity and durability, and thus, will be useful as a chiral-selective catalyst or a material of separating an isomeric mixture.Type: ApplicationFiled: January 7, 2005Publication date: January 15, 2009Inventors: Dong Han Bae, Chang Ick Lee, Seung Kwon Yang, Kyoung Tai No, Suk Kyu Chang, Byung Hee Seo, Jung Sup Kim, Jong Won Kim, Mee Kyung Song
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Publication number: 20070208594Abstract: Disclosed is a method for electronic examination of medical fees, and more particularly to a method for electronic examination of medical fees using a system for electronic examination of medical fees. The system includes a transmit/receive server, a bill examination server, a management terminal and examiner terminals, and communicates with each medical institution server and a national health insurance corporation server. The bill examination server checks any error in medical bills and specifications received from each medical institution server through description inspection, automatic inspection, specialist inspection and computational examination. The bill examination server returns, corrects or adjusts any erroneous bill or specification, or inserts a message into the erroneous bill or specification. The management terminal distributes medical bills and specifications on which computational examination has been completed to the examiner terminals.Type: ApplicationFiled: August 31, 2006Publication date: September 6, 2007Inventors: Young Kwon Yang, Jin Seong Kim, Ji Seung Lee, Keun Ho Bang, Byoung Min Lee
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Patent number: 7259067Abstract: The present invention relates to a method for manufacturing a flash memory device. A plurality of conductive layers and dielectric layers are etched in a single etch apparatus, thus forming a control gate and a floating gate. In a gate formation process in which a thickness of a floating gate is over 1500 ?, problems in short process time and short mass production margin in an existing process can be solved while completely stripping a dielectric layer fence.Type: GrantFiled: June 21, 2004Date of Patent: August 21, 2007Assignee: Hynix Semiconductor Inc.Inventor: In Kwon Yang
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Patent number: 7122443Abstract: A method of fabricating a flash memory device is disclosed where a trench formation process and a wall oxide film formation process are performed separately depending on a pattern density, and wall oxide films are formed with different thicknesses. Accordingly, an increase in a thickness of the wall oxide films due to a smiling effect of tunnel oxide films by a wall oxidization process is prevented and reliability of a device can thus be improved.Type: GrantFiled: December 17, 2004Date of Patent: October 17, 2006Assignee: Hynix Semiconductor Inc.Inventor: In Kwon Yang
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Patent number: 7052960Abstract: A method of manufacturing a flash memory device by carrying out the process of shallow trench isolation (STI) in a memory cell region, so that it decreases an aspect ratio of pattern by forming a field isolation film so as to reduce gap-filling defects due to high density plasma (HDP) and to prevent the smiling effect at a tunnel oxide film so as to improve a programming speed of the flash memory device. The method also conducts the process of self-aligned shallow trench isolation (SA-STI) in a peripheral circuit region by forming a field isolation film, so that it prevents degradation in the characteristics of high and low voltage gate oxide films.Type: GrantFiled: May 11, 2005Date of Patent: May 30, 2006Assignee: Hynix Semiconductor Inc.Inventor: In Kwon Yang
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Publication number: 20060088965Abstract: A method of fabricating a flash memory device is disclosed where a trench formation process and a wall oxide film formation process are performed separately depending on a pattern density, and wall oxide films are formed with different thicknesses. Accordingly, an increase in a thickness of the wall oxide films due to a smiling effect of tunnel oxide films by a wall oxidization process is prevented and reliability of a device can thus be improved.Type: ApplicationFiled: December 17, 2004Publication date: April 27, 2006Applicant: HYNIX SEMICONDUCTOR INC.Inventor: In Kwon Yang
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Publication number: 20060019446Abstract: A method of manufacturing a flash memory device by carrying out the process of shallow trench isolation (STI) in a memory cell region, so that it decreases an aspect ratio of pattern by forming a field isolation film so as to reduce gap-filling defects due to high density plasma (HDP) and to prevent the smiling effect at a tunnel oxide film so as to improve a programming speed of the flash memory device. The method also conducts the process of self-aligned shallow trench isolation (SA-STI) in a peripheral circuit region by forming a field isolation film, so that it prevents degradation in the characteristics of high and low voltage gate oxide films.Type: ApplicationFiled: May 11, 2005Publication date: January 26, 2006Inventor: In Kwon Yang
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Patent number: 6987046Abstract: The present invention discloses a method for manufacturing a flash memory device including the steps of: sequentially forming a first polysilicon film for a floating gate electrode, a first oxide film, a polysilicon film for a hard mask and a second oxide film on a semiconductor substrate; etching and patterning the second oxide film and the polysilicon film for the hard mask, by forming photoresist patterns on a predetermined region of the second oxide film, and removing the photoresist patterns; forming spacers on the sidewalls of the polysilicon film for the hard mask, by forming and etching a polysilicon film for forming spacers on the whole surface of the resulting structure; removing the exposed first oxide film and a predetermined thickness of second oxide film formed on the patterned polysilicon film for the hard mask; forming floating gate electrode patterns by performing first and second etching processes by using the patterned polysilicon film for the hard mask and the spacers as an etch mask; perfType: GrantFiled: June 30, 2004Date of Patent: January 17, 2006Assignee: Hynix Semiconductor Inc.Inventors: In Kwon Yang, Byoung Ki Lee, Jung Woong Lee
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Publication number: 20050095784Abstract: The present invention relates to a method for manufacturing a flash memory device. A plurality of conductive layers and dielectric layers are etched in- a single etch apparatus, thus forming a control gate and a floating gate. In a gate formation process in which a thickness of a floating gate is over 1500 ?, problems in short process time and short mass production margin in an existing process can be solved while completely stripping a dielectric layer fence.Type: ApplicationFiled: June 21, 2004Publication date: May 5, 2005Inventor: In Kwon Yang
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Patent number: 6852595Abstract: Methods of manufacturing flash memory cells. During a cleaning process after an etching process for forming a control gate is performed, polymer remains at the sidewall of a tungsten silicide layer. Therefore, the sidewall of the tungsten silicide layer is protected from a subsequent a self-aligned etching process. In addition, upon a self-aligned etching process, the etch selective ratio of the tungsten silicide layer to a polysilicon layer is sufficiently obtained using a mixed gas of HBr/O2. Therefore, etching damage to the sidewall of the tungsten silicide layer can be prevented. As a result, reliability of the process and an electrical characteristic of the resulting device are improved.Type: GrantFiled: December 5, 2002Date of Patent: February 8, 2005Assignee: Hynix SemiconductorInventor: In Kwon Yang
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Publication number: 20030134472Abstract: Methods of manufacturing flash memory cells. During a cleaning process after an etching process for forming a control gate is performed, polymer remains at the sidewall of a tungsten silicide layer. Therefore, the sidewall of the tungsten silicide layer is protected from a subsequent a self-aligned etching process. In addition, upon a self-aligned etching process, the etch selective ratio of the tungsten silicide layer to a polysilicon layer is sufficiently obtained using a mixed gas of HBr/O2. Therefore, etching damage to the sidewall of the tungsten silicide layer can be prevented. As a result, reliability of the process and an electrical characteristic of the resulting device are improved.Type: ApplicationFiled: December 5, 2002Publication date: July 17, 2003Inventor: In Kwon Yang
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Patent number: 6477001Abstract: An auto-balancing disk drive apparatus is disclosed which makes it possible to decrease the installation space of an auto balancing unit thereof which is capable of automatically preventing an up and down movement of a disk when the disk is rotated at a high speed, reducing the driving force which is needed for the rotation of the disk and auto balancing unit, and reducing the noise and vibration which occur at the auto balancing unit. The disk drive apparatus includes a motor generating a rotational force with respect to a rotary shaft, and an auto balancing unit installed radially laterally and co-planar with respect to the rotary shaft for automatically correcting an unbalanced state of a rotation member when an unbalanced state occurs at the rotation member.Type: GrantFiled: June 1, 1999Date of Patent: November 5, 2002Assignee: LG Electronics Inc.Inventors: Hyung Kwon Yang, Chung Ku Yie
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Patent number: 5235421Abstract: An encoding device for selectively transmitting not only the picture of a 1.times.NTSC level but also the superhigh resolution pictures of 2.times.NTSC, 3.times.NTSC or 4.times.NTSC levels, by reducing the bandwidth of sub-bands and by using a sub-band coding technique in the case where the bandwidth of channels is restricted. The device includes a 3-dimensional low pass filter 4 for separating the signal output from an A/D converter 3 into 3-dimensional sub-blocks of chrominance signal, and a matrix circuit 5 for separating the signals output from the A/D converter 3 into luminance and chrominance signals. Furthermore, a horizontal, vertical and temporal QMFs 6, 8 and 10 divides the luminance signal into a plurality of horizontal, vertical and temporal sub-blocks in the direction of a horizontal, vertical and temporal axes and compresses the above sub-blocks. A motion detector 15 detects a motion signal corresponding to a still region, a semi-motion region and a motion region.Type: GrantFiled: June 14, 1991Date of Patent: August 10, 1993Assignee: SamSung Electronics, Ltd.Inventor: Tae-Kwon Yang
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Patent number: 5202755Abstract: An encoding system of a simulcast high definition television and a method thereof capable of encoding an image signal of high picture quality and an aural signal of high tone quality. In order to improve a MIT proposal system, the bandwidth of a baseband image signal of a high definition television is compressed by a three-dimensional sub-band coding, divided sub-blocks are adaptively selected and modulated. Thereafter, the adaptive modulated signal is scrambled, transmission-gamma-processed, data-under-processed and processed by a double side band-quadrature modulation (DSB-QM). Thus, good picture quality in comparison with the MIT proposal system is obtainable.Type: GrantFiled: December 24, 1991Date of Patent: April 13, 1993Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Kwon Yang, Dong-Il Song
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Patent number: 5093723Abstract: A method for 90.degree. phase-shift modulation and demodulation in a circuit having a PLL. A phase-shift of 90.degree. between a main and an additional signal is provided. The method comprises the steps of: modulating by (a) selecting a specified position and inserting a pilot signal, (b) giving the phase-shift of 90.degree. to an image carrier wave and (c) generating a modulated signal; and demodulating by (d) receiving the modulated signal and demodulating the main and additional signals having phase-shift of 90.degree. to each other, (e) generating a frequency locked to the transmitted signal and controlling an output of a voltage controlled oscillator and reproducing the main and additional signals of step (d).Type: GrantFiled: July 6, 1990Date of Patent: March 3, 1992Assignee: Samsung Electronics Co., Ltd.Inventor: Tae-Kwon Yang