Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked over the first semiconductor device. The second semiconductor device is electrically connected to the first semiconductor device via a plurality of through electrodes. In a test mode, the first semiconductor device is configured to drive a first pattern of logic levels and a second pattern of logic levels through the plurality of through electrodes, configured to compare logic levels of a plurality of test data generated by the first and second patterns from the first and second semiconductor devices to generate a detection signal indicating that the plurality of through electrodes operated normally or abnormally.

Abstract: The present disclosure relates to an intermediate connection structure of a power cable, which is capable of reducing heating of a connecting part of conductors of a pair of power cables connected through a joint box, enhancing a connected state of the conductors, and minimizing a diameter of the conductor connection part.

Abstract: The present invention relates to a hydrogel composition for preventing tissue adhesion, and a preparation method therefor, and the hydrogel composition is composed of a polyethylene oxide-polypropylene oxide-polyethylene oxide terpolymer, a water-insoluble hyaluronic acid, sodium alginate and purified water and is prepared through the preparation method comprising: a copolymer melting step of heating, for one to two hours at a temperature of 60-100° C., a polyethylene oxide-polypropylene oxide-polyethylene oxide terpolymer having a molecular weight of 1-500 kDa, and melting same; a hyaluronic acid mixing step of mixing a molten product, having been prepared through the copolymer melting step, with a water-insoluble hyaluronic acid and stirring same at a temperature of 10-20° C.; and a sodium alginate mixing step of mixing a mixture, having been prepared through the hyaluronic acid mixing step, with sodium alginate and stirring same at a temperature of 5-20° C.

Abstract: The present invention relates to a transgenic cloned pig for xenotransplantation in which porcine endogenous retrovirus (RUN) EnvC is negative, ?1,3-galactosyltransferase (GGTA1), CMP-N-acetylneuraminic acid hydroxylase (CMAH), isoglobotrihexosylceramide synthase (iGb3s), and beta-I,4-N-acetyl-galactosaminyl transferase2 (?4GalNT2) are knocked out, and human CD46 and thrombomodulin (TBM) genes are expressed, and to a method of preparing the transgenic cloned pig. The transgenic cloned pig according to the present invention may overcome hyperacute and antigen-antibody mediated immune rejection reaction, immune rejection reaction due to blood coagulation, and immune rejection reaction due to complement activity, without causing transfer of porcine endogenous retrovirus that occurs in xenotransplantation. Therefore, the transgenic cloned pig according to the present invention may be usefully utilized as a donor animal for xenotransplantation of organs and cells.

Abstract: An electronic device includes a replica delay circuit configured to generate a delayed error check signal by delaying a first error check signal including error information of first data stored in a first memory region. The electronic device also includes an error sum signal generation circuit configured to generate an error sum signal by summing a second error check signal including error information of second data stored in a second memory region and the delayed error check signal.

Abstract: The present disclosure relates to a power cable joint system capable of minimizing expansion, deformation or damage of a metal sheath restoration layer, which is formed of a material such as lead sheath, due to internal expansion due to heat generated in an intermediate connection part of the power cable joint system.

Abstract: A method of building a machine learning pipeline for predicting the efficacy of anti-epilepsy drug treatment regimens is provided.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs an error check enablement signal, an input clock signal, and input data to the second semiconductor device. The first semiconductor device receives an error check signal from the second semiconductor device. The second semiconductor device performs an error check operation for the input data based on the error check enablement signal and the input clock signal to generate the error check signal which is enabled when an error in the input data occurs.

Abstract: A semiconductor device includes an error detection circuit configured to generate fixed data by fixing any one of a first group and a second group included in internal data to a preset level based on a burst chop signal and an internal command address in response to a read command, and generate an error detection signal by detecting an error of the fixed data; and a data output circuit configured to generate latch data by latching the internal data based on a first latch output control signal, and generate output data by serializing the latch data and the error detection signal based on a second latch output control signal.

Abstract: The present invention disclosure relates to an intermediate connection structure of a power cable, which is capable of reducing heating of a connecting part of conductors of a pair of power cables connected through a joint box, enhancing a connected state of the conductors, and minimizing a diameter of the conductor connection part.

Abstract: An electronic device includes a replica delay circuit configured to generate a delayed error check signal by delaying a first error check signal including error information of first data stored in a first memory region. The electronic device also includes an error sum signal generation circuit configured to generate an error sum signal by summing a second error check signal including error information of second data stored in a second memory region and the delayed error check signal.

Abstract: A semiconductor device includes a master chip and a first slave chip. The master chip outputs a write signal or read signal and a chip identification (ID) signal and outputs data through a transmitter activated by the write signal or receives data through a receiver activated by the read signal. The first slave chip enters a write operation according to the write signal and activates a first receiver to store the data when the chip ID signal has a first logic level combination. The first slave chip enters a read operation according to the read signal and configured to activate a first transmitter to output the data when the chip ID signal has a first logic level combination. The master chip and the first slave chip are vertically stacked and are electrically connected to each other by a plurality of through electrodes penetrating the first slave chip.

Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked over the first semiconductor device. The second semiconductor device is electrically connected to the first semiconductor device via a plurality of through electrodes. In a test mode, the first semiconductor device is configured to drive a first pattern of logic levels and a second pattern of logic levels through the plurality of through electrodes configured to compare logic levels of a plurality of test data generated by the first and second patterns from the first and second semiconductor devices to generate a detection signal indicating that the plurality of through electrodes operated normally or abnormally.

Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked over the first semiconductor device. The second semiconductor device is electrically connected to the first semiconductor device via a plurality of through electrodes. In a test mode, the first semiconductor device is configured to drive a first pattern of logic levels and a second pattern of logic levels through the plurality of through electrodes, configured to compare logic levels of a plurality of test data generated by the first and second patterns from the first and second semiconductor devices to generate a detection signal indicating that the plurality of through electrodes operated normally or abnormally.

Abstract: An integrated circuit includes: a phase-shifted data signal generation circuit configured to generate a plurality of phase-shifted data signals from an input data signal based on at least one phase-shifted clock signal; a synchronization circuit configured to generate a plurality of synchronization data signals by applying the at least one phase-shifted clock signal to the plurality of phase-shifted data signals provided by the phase-shifted data signal generation circuit; and a control signal generation circuit configured to perform logic operations on the plurality of synchronization data signals to generate a phase control signal for controlling a phase of the at least one phase-shifted clock signal, and generate a frequency control signal for controlling a frequency of the at least one phase-shifted clock signal.

Abstract: A semiconductor system including a semiconductor device configured to operate in various modes to generate output data having different patterns.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A semiconductor device includes a master chip and a first slave chip. The master chip outputs a write signal or read signal and a chip identification (ID) signal and outputs data through a transmitter activated by the write signal or receives data through a receiver activated by the read signal. The first slave chip enters a write operation according to the write signal and activates a first receiver to store the data when the chip ID signal has a first logic level combination. The first slave chip enters a read operation according to the read signal and configured to activate a first transmitter to output the data when the chip ID signal has a first logic level combination. The master chip and the first slave chip are vertically stacked and are electrically connected to each other by a plurality of through electrodes penetrating the first slave chip.

Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked and coupled through a unidirectional through electrode and a plurality of bidirectional through electrodes, wherein a through electrode in which a failure has occurred among the unidirectional through electrode and the plurality of bidirectional through electrodes is replaced based on a plurality of transfer control signals. The plurality of transfer control signals including failure information on the unidirectional through electrode and the plurality of bidirectional through electrodes.

Abstract: The present disclosure provides a surface-modified alginate micro-capsule having a core-shell structure in which a core is fluidizable phase alginate, and a shell is alginate hydrogel crosslinked with epigallocatechin gallate dimer, a preparation method thereof, and a cell encapsulation method using the same.