Patents by Inventor In-Seak Hwang
In-Seak Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10438799Abstract: A method of fabricating semiconductor devices includes sequentially forming a gate layer and a mandrel layer on a substrate, forming a first photoresist on the mandrel layer, forming a mandrel pattern by at least partially removing the mandrel layer using the first photoresist as a mask, forming a spacer pattern that comprises a first mandrel spacer located on a side of a first mandrel included in the mandrel pattern and a second mandrel spacer located on the other side of the first mandrel, forming a sacrificial layer that covers the first and second mandrel spacers after removing the mandrel pattern, forming a second photoresist including a bridge pattern overlapping parts of the first and second mandrel spacers on the sacrificial layer; and forming a gate pattern by at least partially removing the gate layer using the first and second mandrel spacers and the second photoresist as a mask.Type: GrantFiled: March 29, 2017Date of Patent: October 8, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Jine Park, Yong Sun Ko, In Seak Hwang
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Patent number: 10109529Abstract: A semiconductor device including a direct contact and a bit line in a cell array region and a gate electrode structure in a peripheral circuit region, and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate including a cell array region including a first active region and a peripheral circuit region including a second active region, a first insulating layer on the substrate, the first insulating layer including contact holes exposing the first active region, a direct contact in the contact holes, wherein a direct contact is connected to the first active region, a bit line connected to the direct contact in the cell array region and extending in a first direction, and a gate insulating layer and a gate electrode structure, wherein a dummy conductive layer including substantially the same material as the direct contact is in the peripheral circuit region.Type: GrantFiled: June 17, 2016Date of Patent: October 23, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Young-ho Koh, Byoung-ho Kwon, Yang-hee Lee, Young-kuk Kim, In-seak Hwang, Bo-un Yoon
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Patent number: 9985106Abstract: Semiconductor devices may include a field insulating layer that is on a substrate, a gate structure that is on the substrate and separated from the field insulating layer, a first spacer structure that is on sidewalls and a lower surface of the gate structure and is separated from the field insulating layer, and a second spacer structure that is on a part of an upper surface of the field insulating layer that is overlapped by the gate structure.Type: GrantFiled: January 31, 2017Date of Patent: May 29, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Jine Park, Yong Sun Ko, In Seak Hwang
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Patent number: 9960169Abstract: In a method of manufacturing a semiconductor device, mask patterns are formed on a semiconductor substrate. An organic layer is formed on the semiconductor substrate to cover the mask patterns. An upper portion of the organic layer is planarized using a polishing composition. The polishing composition includes an oxidizing agent and is devoid of abrasive particles.Type: GrantFiled: August 22, 2016Date of Patent: May 1, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Seok Lee, Byoung-Ho Kwon, Sang-Kyun Kim, Yun-Jeong Kim, Seung-Ho Park, Hao Cui, In-Seak Hwang
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Publication number: 20180040483Abstract: A method of fabricating semiconductor devices includes sequentially forming a gate layer and a mandrel layer on a substrate, forming a first photoresist on the mandrel layer, forming a mandrel pattern by at least partially removing the mandrel layer using the first photoresist as a mask, forming a spacer pattern that comprises a first mandrel spacer located on a side of a first mandrel included in the mandrel pattern and a second mandrel spacer located on the other side of the first mandrel, forming a sacrificial layer that covers the first and second mandrel spacers after removing the mandrel pattern, forming a second photoresist including a bridge pattern overlapping parts of the first and second mandrel spacers on the sacrificial layer; and forming a gate pattern by at least partially removing the gate layer using the first and second mandrel spacers and the second photoresist as a mask.Type: ApplicationFiled: March 29, 2017Publication date: February 8, 2018Inventors: Sang Jine Park, Yong Sun Ko, In Seak Hwang
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Publication number: 20180040707Abstract: Semiconductor devices may include a field insulating layer that is on a substrate, a gate structure that is on the substrate and separated from the field insulating layer, a first spacer structure that is on sidewalls and a lower surface of the gate structure and is separated from the field insulating layer, and a second spacer structure that is on a part of an upper surface of the field insulating layer that is overlapped by the gate structure.Type: ApplicationFiled: January 31, 2017Publication date: February 8, 2018Inventors: Sang Jine Park, Yong Sun Ko, In Seak Hwang
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Patent number: 9659940Abstract: A method of manufacturing a semiconductor device includes: preparing a wafer in which a first cell area and a second cell area are defined; forming a bottom electrode structure in the first cell area and a dummy structure located in the second cell area; and sequentially forming a dielectric layer and a top electrode on the bottom electrode structure and the dummy structure, wherein the bottom electrode structure includes a plurality of bottom electrodes extending in a first direction in the first cell area and first and second supporters to support the plurality of bottom electrodes, wherein the dummy structure includes a first mold film, a first supporter film, a second mold film, and a second supporter film that are sequentially formed to cover the second cell area, and the second supporter and the second supporter film are at a same level relative to the wafer.Type: GrantFiled: July 6, 2016Date of Patent: May 23, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Hye-sung Park, In-seak Hwang, Bo-un Yoon, Byoung-ho Kwon, Jong-hyuk Park, Jae-hee Kim, Myung-jae Jang
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Publication number: 20170098653Abstract: Methods of manufacturing a semiconductor device are provided. Methods may include forming first to third regions having densities different from one another on a substrate, covering the first to third regions to form an upper interlayer insulating film including a low step portion and a high step portion higher than the low step portion, forming an organic film on the upper interlayer insulating film, removing a part of the organic film to expose an upper surface of the high step portion, removing the high step portion so that an upper surface of the high step portion is disposed on at least the same line as the organic film disposed on the upper surface of the lower step portion, removing the remaining part of the organic film to expose the upper surface of the upper interlayer insulating film and flattening the upper surface of the upper interlayer insulating film.Type: ApplicationFiled: June 15, 2016Publication date: April 6, 2017Inventors: Young-Ho Koh, Hye-Sung Park, Byoung-Ho Kwon, Jong-Hyuk Park, Bo-Un Yoon, ln-Seak Hwang
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Publication number: 20170084710Abstract: A semiconductor device including a direct contact and a bit line in a cell array region and a gate electrode structure in a peripheral circuit region, and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate including a cell array region including a first active region and a peripheral circuit region including a second active region, a first insulating layer on the substrate, the first insulating layer including contact holes exposing the first active region, a direct contact in the contact holes, wherein a direct contact is connected to the first active region, a bit line connected to the direct contact in the cell array region and extending in a first direction, and a gate insulating layer and a gate electrode structure, wherein a dummy conductive layer including substantially the same material as the direct contact is in the peripheral circuit region.Type: ApplicationFiled: June 17, 2016Publication date: March 23, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Young-ho Koh, Byoung-ho Kwon, Yang-hee Lee, Young-kuk Kim, In-seak Hwang, Bo-un Yoon
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Publication number: 20170077103Abstract: A method of manufacturing a semiconductor device includes: preparing a wafer in which a first cell area and a second cell area are defined; forming a bottom electrode structure in the first cell area and a dummy structure located in the second cell area; and sequentially forming a dielectric layer and a top electrode on the bottom electrode structure and the dummy structure, wherein the bottom electrode structure includes a plurality of bottom electrodes extending in a first direction in the first cell area and first and second supporters to support the plurality of bottom electrodes, wherein the dummy structure includes a first mold film, a first supporter film, a second mold film, and a second supporter film that are sequentially formed to cover the second cell area, and the second supporter and the second supporter film are at a same level relative to the wafer.Type: ApplicationFiled: July 6, 2016Publication date: March 16, 2017Inventors: Hye-sung Park, ln-seak Hwang, Bo-un Yoon, Byoung-ho Kwon, Jong-hyuk Park, Jae-hee Kim, Myung-jae Jang
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Publication number: 20170062437Abstract: In a method of manufacturing a semiconductor device, mask patterns are formed on a semiconductor substrate. An organic layer is formed on the semiconductor substrate to cover the mask patterns. An upper portion of the organic layer is planarized using a polishing composition. The polishing composition includes an oxidizing agent and is devoid of abrasive particles.Type: ApplicationFiled: August 22, 2016Publication date: March 2, 2017Inventors: Jun-Seok Lee, Byoung-Ho Kwon, Sang-Kyun Kim, Yun-Jeong Kim, Seung-Ho Park, Hao Cui, ln-Seak Hwang
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Patent number: 9390961Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first bit line structure extending in a first direction, a second bit line structure extending in the first direction and spaced apart from the first bit line structure, a storage contact plug located between the first bit line structure and the second bit line structure, and extending in a second direction perpendicular to the first direction, a first plug insulator located between the first bit line structure and the second bit line structure, and configured to contact a side surface extending in the second direction of the storage contact plug, and a plug isolation pattern located between the first bit line structure and the first plug insulator.Type: GrantFiled: September 10, 2014Date of Patent: July 12, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Mong-Sup Lee, Byoung-Yong Gwak, Byung-Ho Kwak, Yoon-Kyung Kim, Tae-Joon Park, Byung-Sul Ryu, In-Seak Hwang
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Publication number: 20160079260Abstract: A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed.Type: ApplicationFiled: June 3, 2015Publication date: March 17, 2016Inventors: Jin-woo Bae, Byoung-ho Kwon, Jong-hyuk Park, Hye-sung Park, Jun-seok Lee, Ki-vin Im, Hee-sook Cheon, In-seak Hwang
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Patent number: 9269720Abstract: A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed.Type: GrantFiled: June 3, 2015Date of Patent: February 23, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-woo Bae, Byoung-ho Kwon, Jong-hyuk Park, Hye-sung Park, Jun-seok Lee, Ki-vin Im, Hee-sook Cheon, In-seak Hwang
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Publication number: 20160027786Abstract: A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.Type: ApplicationFiled: October 5, 2015Publication date: January 28, 2016Inventors: Young-Kuk KIM, Ki-Vin IM, Han-Jin LIM, In-Seak HWANG
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Patent number: 9240414Abstract: A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.Type: GrantFiled: October 5, 2015Date of Patent: January 19, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Kuk Kim, Ki-Vin Im, Han-Jin Lim, In-Seak Hwang
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Patent number: 9184227Abstract: A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.Type: GrantFiled: October 31, 2014Date of Patent: November 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Kuk Kim, Ki-Vin Im, Han-Jin Lim, In-Seak Hwang
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Publication number: 20150311276Abstract: A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.Type: ApplicationFiled: October 31, 2014Publication date: October 29, 2015Inventors: YOUNG-KUK KIM, Ki-Vin Im, Han-Jin Lim, In-Seak Hwang
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Publication number: 20150311297Abstract: Provided are a semiconductor device and a method of forming thereof. The semiconductor device includes a substrate having an isolating trench defining active areas, gate structures formed in the active area and crossing the isolating trench, a first protection layer formed on the active area of the substrate, and a second protection layer formed on the first protection layer, wherein, in a first isolating area in which the gate structure and the isolating trench cross, the first protection layer is conformally formed on an inner wall and bottom of the isolating trench, and the second protection layer is formed on the first protection layer formed on the bottom of the isolating trench.Type: ApplicationFiled: December 1, 2014Publication date: October 29, 2015Inventors: Badro IM, Ki-Vin IM, Young-kuk KIM, Han-jin LIM, In-Seak HWANG
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Publication number: 20150171163Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first bit line structure extending in a first direction, a second bit line structure extending in the first direction and spaced apart from the first bit line structure, a storage contact plug located between the first bit line structure and the second bit line structure, and extending in a second direction perpendicular to the first direction, a first plug insulator located between the first bit line structure and the second bit line structure, and configured to contact a side surface extending in the second direction of the storage contact plug, and a plug isolation pattern located between the first bit line structure and the first plug insulator.Type: ApplicationFiled: September 10, 2014Publication date: June 18, 2015Inventors: Mong-Sup LEE, Byoung-Yong GWAK, Byung-Ho KWAK, Yoon-Kyung KIM, Tae-Joon PARK, Byung-Sul RYU, In-Seak HWANG