Abstract: An electronic device is provided. The electronic device includes a housing having an opening, a roll installed in the housing, a flexible display configured to be wound on the roll and to be withdrawn from the housing through the opening in accordance with a rotating direction of the roll. The electronic device further includes moveable housing parts and a housing guide configured to guide and retract at least one part of the housing as space within the housing becomes available due to withdrawal of the flexible display, so that a height, width and/or overall size of the housing is reduced when the flexible display is withdrawn through the opening and extended outside of the housing.

Abstract: An embodiment includes a method of texturing a semiconductor substrate, a semiconductor substrate manufactured using the method, and a solar cell including the semiconductor substrate, the method including: forming metal nanoparticles on a semiconductor substrate, primarily etching the semiconductor substrate, removing the metal nanoparticles, and secondarily etching the primarily etched semiconductor substrate to form nanostructures.

Abstract: A data processing device includes a plurality of variable nodes configured to receive and store a plurality of target bits; a plurality of check nodes each configured to receive stored target bits from one or more corresponding variable nodes of the plurality of variable nodes, check whether received target bits have an error bit, and transmit a check result to the corresponding variable nodes; and a group state value manager configured to determine group state values of variable node groups into which the plurality of variable nodes are grouped.

Abstract: Provided herein may be an error correction decoder, an error correction circuit having the error correction decoder, and a method of operating the error correction decoder. The error correction decoder may include a calculator configured to output an error correction message by performing an iterative decoding operation on a first codeword, a syndrome generator configured to generate a syndrome by calculating the error correction message and a parity check matrix and to output a number of iterations representing the number of times the iterative decoding operation has been performed, and an unsatisfied check node (UCN) value representing the number of unsatisfied check nodes in the syndrome, and a speed selector configured to output a speed code for controlling a speed of the iterative decoding operation depending on the number of iterations and the UCN value.

Abstract: The present invention is advantageous in that the shape of the catheter can be sensed by detecting the position of bending of the catheter body, the direction thereof, the angle thereof, and the curvature thereof through a triplet calculation of information regarding three wavelengths that have undergone a transition along respective FBGs provided on three optical cores.

Abstract: The present disclosure relates to a compound represented by Formula 1 and an organic light emitting device using the same. The compound used as a material of an organic material layer of the organic light emitting device provides improved efficiency, low driving voltage, and improved lifetime characteristic.

Abstract: A paste for a reference electrode according to an embodiment of the present disclosure includes silver chloride powder and a carbon-based conductive material. The carbon-based conductive material may include at least one compound selected from the group consisting of carbon nanotubes, graphite, graphene, and carbon black. The reference electrode formed of the paste for a reference electrode according to an exemplary embodiment may provide improved mechanical properties and electrochemical properties.

Abstract: A processing-in-memory (PIM) device includes a multiplication-and-accumulation (MAC) circuit, a memory circuit, and an address pipeline circuit. The MAC circuit is configured to perform a MAC arithmetic operation or an element-wise multiplication (EWM) calculation for first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the MAC circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

Abstract: In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.

Abstract: An embodiment of the present invention relates to a coupling structure of a battery pack, and the objective of the present invention is to provide a battery pack which can stably and easily fix a bus bar. To this end, provided is a battery pack comprising: a base defining the entire bottom surface; a battery module installed on the base; a module fixing part positioned around a side surface and an upper surface of the battery module and coupled to the base; a first bus bar fixing part coupled to the module fixing part; a bus bar disposed on the first bus bar fixing part and electrically connectable to the battery module; and a second bus bar fixing part installed to cover the bus bar and fixed to the first bus bar fixing part.

Abstract: An aerosol generating system may include a plurality of susceptors having different resonance frequencies and configured to heat different portions of a cigarette accommodated in an aerosol generating device, a coil configured to heat the plurality of susceptors, a plurality of capacitors connected to the coil, and a processor configured to determine a combination of capacitors through which current applied to the coil is to pass from among the plurality of capacitors, and heat a susceptor corresponding to a resonance frequency according to the combination by applying current to the coil according to the combination.

Abstract: In accordance with an embodiment of the present disclosure, a semiconductor system includes a first semiconductor device coupled to a first transmission line, and configured to transmit a first packet to a second transmission line on the basis of first destination information of the first packet received through the first transmission line; a second semiconductor device coupled to the first semiconductor device through the second transmission line, and configured to transmit a second packet to a third transmission line on the basis of second destination information of the second packet received through the second transmission line; and a third semiconductor device coupled to the second semiconductor device through the third transmission line, coupled to the first semiconductor device through the first transmission line, and configured to transmit a third packet to the first transmission line on the basis of third destination information of the third packet received through the third transmission line.

Abstract: A display device includes a display panel including a gate line, a data line, and a pixel electrically connected to the gate line and the data line and that displays an image based on input image data, a gate driver which outputs a gate signal to the gate line, a data driver which outputs a data voltage to the data line, and a driving controller which controls the gate driver and the data driver. The pixel includes a first pixel that emits light in a first mode and does not emit light in a second mode and a second pixel that emits light in both the first mode and the second mode, where the second pixel has a narrower viewing angle than the first pixel. The gate line includes a first gate line connected only to the first pixel and a second gate line connected only to the second pixel.

Abstract: The present invention is a system for three-dimensionally mapping a heart, comprising: a mapping catheter including three or more optical cores each of which has a plurality of FBGs disposed in the lengthwise direction of a catheter body, and a plurality of electrodes disposed in the lengthwise direction of the catheter body and exposed on the outer circumferential surface of the catheter body, wherein the electrodes make contact with the inner wall of the heart; and a mapping processor for calculating coordinates of the FBGs by wavelength information of reflected light received from the three or more optical cores, and calculating coordinates of the electrodes from the coordinates of the FBGs so as to build a three-dimensional shape of the heart by using a sample point at which the plurality of electrodes make contact.

Abstract: A method for manufacturing a lower housing of a battery pack having an embedded cooling pipe comprises the steps of: preparing a cooling pipe, which protrudes to the outside of the lower housing so as to be insert-connected to an external quick connector, includes a locking protrusion having a first outer diameter at a quick connector insertion part to be connected to the quick connector, and a second outer diameter for enabling the protrusion to be fixed to the quick connector in the inward direction in a first length at the end of the quick connector insertion part, and has a joint part which has a predetermined length and a third outer diameter corresponding to the second outer diameter in the inward direction in a second length longer than the first length at the end of the quick connector insertion part, and which is to be disposed over a cooling pipe inlet of the lower housing; preparing a slider including one or more pipe insertion parts having inner diameters corresponding to the third outer diameter

Abstract: A processing-in-memory (PIM) device includes a multiplier circuit, a memory circuit, and an address pipeline circuit. The multiplier circuit is configured to perform an element-wise multiplication (EWM) calculation of first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the multiplier circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

Abstract: The present disclosure relates to a continuous blood sugar measuring sensor member, wherein: since an electrode layer formed on one surface of a substrate is connected to a sensor contact point part on the other surface of the substrate through a via hole and thus two electrode layers may be formed on different opposite surfaces without having to be formed on the same surface of the substrate, the width of the substrate may be further reduced and an overall minimized and simplified structure may be ensured; since an electrode connection layer formed at the via hole is not formed in a shape of filling the via hole but is formed only on the inner circumferential surface, a filling defect occurring in a process of filling the via hole and a fault in electrical connection according thereto may be prevented and thus a more stable structure may be ensured; and since a plurality of via holes are formed, despite damage to or the occurrence of a defect in an electrode connection layer formed at one of the via holes, e

Abstract: A silencer for a leaf spring for a commercial vehicle is provided. The silencer includes an upper rubber body having defined therein a fitting hole into which a second leaf spring is press-fitted, with a top surface of the upper rubber body serving as a contact surface in contact with a first leaf spring, and a lower rubber body having defined therein an accommodation space, with a first buffering protrusion being provided on a bottom surface of the lower rubber body such that a third leaf spring is able to be in contact with the first buffering protrusion.

Abstract: A neuromorphic device includes: a neuron block unit including a plurality of neurons; a synapse block unit including a plurality of synapses; and a topology block unit including a plurality of parallel Look-Up Table (LUT) modules including pre and post neuron elements configured with addresses of a presynaptic neuron and a postsynaptic neuron. Each of the plurality of neurons has an intrinsic address, each of the plurality of synapses has an intrinsic address. The parallel LUT module is partitioned based on a first synapse address among synapse addresses, and each of the partitions is indexed based on a second synapse address among the synapse addresses.

Abstract: A processing-in-memory (PIM) device includes a multiplier circuit, a memory circuit, and an address pipeline circuit. The multiplier circuit is configured to perform an element-wise multiplication (EWM) calculation of first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the multiplier circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.