Patents by Inventor Inseok Yang

Inseok Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240122045
    Abstract: A display device includes: a display panel including a first light emitting area to emit a source light; a barrier wall on the display panel, and having a first opening corresponding to the first light emitting area; a first light control pattern in the first opening; and a light shielding pattern between the display panel and the barrier wall, and overlapping with the barrier wall and the first opening. The light shielding pattern overlaps with a portion of the first light control pattern.
    Type: Application
    Filed: August 24, 2023
    Publication date: April 11, 2024
    Inventors: GAK SEOK LEE, KEUNCHAN OH, MIN-JAE KIM, KYUNGHAE PARK, JAE CHEOL PARK, INSEOK SONG, JISEONG YANG
  • Patent number: 9698158
    Abstract: A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: July 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-Seok Jung, Changseok Kang, Seungwoo Paek, Inseok Yang, Kyungjoong Joo
  • Publication number: 20160365356
    Abstract: A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.
    Type: Application
    Filed: August 26, 2016
    Publication date: December 15, 2016
    Inventors: Won-Seok JUNG, Changseok KANG, Seungwoo PAEK, Inseok YANG, Kyungjoong JOO
  • Patent number: 9484355
    Abstract: A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: November 1, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-Seok Jung, Changseok Kang, SeungWoo Paek, Inseok Yang, Kyungjoong Joo
  • Patent number: 7677794
    Abstract: The present invention relates to a multi fixed-point cell for calibrating a thermometer and a thermometer calibration apparatus using the same, wherein measuring errors can be checked by using a property of constant temperature of a metal on the basis of a phase transition and wide range of temperature region can be measured by one time calibration, thereby capable of increasing efficiencies of time and cost which are taken for calibration. In a multi fixed-point cell for calibrating a thermometer according to the present invention, a thermometer inserting hole in which a thermometer is inserted is formed at one side and at least two reference material inserting holes in which reference materials having different phase transition temperatures are inserted respectively are formed on a same plane as that of the thermometer inserting hole so as to be spaced apart each other.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: March 16, 2010
    Assignee: Korea Research Institute of Standards and Science
    Inventors: Yong-gyoo Kim, Inseok Yang, Kee sool Gam, Kee hoon Kang
  • Publication number: 20080013591
    Abstract: The present invention relates to a multi fixed-point cell for calibrating a thermometer and a thermometer calibration apparatus using the same, wherein measuring errors can be checked by using a property of constant temperature of a metal on the basis of a phase transition and wide range of temperature region can be measured by one time calibration, thereby capable of increasing efficiencies of time and cost which are taken for calibration. In a multi fixed-point cell for calibrating a thermometer according to the present invention, a thermometer inserting hole in which a thermometer is inserted is formed at one side and at least two reference material inserting holes in which reference materials having different phase transition temperatures are inserted respectively are formed on a same plane as that of the thermometer inserting hole so as to be spaced apart each other.
    Type: Application
    Filed: March 14, 2007
    Publication date: January 17, 2008
    Applicant: Korea Research Institute of Standards and Science
    Inventors: Yong-gyoo Kim, Inseok Yang, Kee sool Gam, Kee hoon Kang