Abstract: An integrated circuit comprises a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric layer formed on the floating gate, and a control gate formed on the inter-gate dielectric layer. The integrated circuit also includes a high and low voltage transistors.

Abstract: Duplex supporting apparatus and method in a base station system which supports a multi-antenna are provided. The duplex supporting apparatus in a base station system which supports K(?1)-ary sectors and M(?1)-ary antennas per sector, includes a plurality of channel cards for generating M-ary data to be sent to the M-ary antennas, exchanging part of the M-ary data with other channel cards, constituting a frame with part of the M-ary data and data received from the other channel cards, and providing the generated frame to a corresponding Radio Frequency (RF) module; and a plurality of RF modules for extracting the M-ary data from a frame of a corresponding channel card among the channel cards, RF-processing the extracted M-ary data, and feeding the processed data to original sectors/antennas.

Abstract: An integrated circuit comprises a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric layer formed on the floating gate, and a control gate formed on the inter-gate dielectric layer. The integrated circuit also includes a high and low voltage transistors.

Abstract: An integrated circuit comprises a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric layer formed on the floating gate, and a control gate formed on the inter-gate dielectric layer. The integrated circuit also includes a high and low voltage transistors.

Abstract: The present invention relates to a turning type charcoal roast board, and more particularly, to a turning type charcoal roast board, wherein if exchange of a used roast board is required during roast of meat using a charcoal fire, new roast rods are placed at an opening of a main body of the roast board in such a manner that the roast rods stored in a roast rod-supplying box are fed via a moving means through users simple operation of a control device for controlling the feeding of the roast rods installed on a main body of the charcoal roast board, and roast rods used at the opening of the main board are transferred to and received in a roast rod-receiving box by means of rotation of the moving means. According to the present invention, the roast board can be rapidly exchanged to prevent meat from being burned, and it is possible to eliminate inconvenience in use due to frequent exchange of roast boards.

Abstract: A method for judging a musical performance is disclosed by the present invention. The method includes entering competitors on a match play board based upon seeding to determine individual matches for competitors. Each competitor in a match performs an individual act. The act of each performer is then judged based upon a plurality of individual performance criteria to determine criteria scores for each competitor. The total scores for each competitor are then determined based upon the determined criteria scores. A winner of each match based upon which competitor received a highest score and the winner of each match is entered on the match play board into a next round of competition. Preferably the performance for the competition is in the musical field of Hip-Hop music. The plurality of individual performance criteria preferably includes at least one of judging by individual judges, noise level of an audience viewing the performances, call in votes and internet votes.

Abstract: An integrated circuit comprises a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric layer formed on the floating gate, and a control gate formed on the inter-gate dielectric layer. The integrated circuit also includes a high and low voltage transistors.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a trench in a first electrically insulating layer and then forming a first electrically conductive layer on a sidewall and bottom of the trench. A dielectric layer is then formed on the first electrically conductive layer. Next, a second electrically conductive layer is formed on the dielectric layer, opposite the first electrically conductive layer. A step is then performed to planarize the first and second electrically conductive layers to define first and second electrodes of a capacitor in the trench. In particular, the step of planarizing the first electrically conductive layer comprises planarizing the first electrically conductive layer to define a first electrode having a U-shaped cross-section. This step results in the formation of a first electrode having a relatively large effective area (which is a function of the depth of the trench) for a given lateral dimension.

Abstract: A method of making a semiconductor device having a thin film resistor, the method comprising the steps of: forming a first polysilicon layer on an upper surface of a field oxide layer formed on a semiconductor substrate; forming a first dielectric layer on a resultant material; ion-implanting an impurity for forming a resistor in the first polysilicon layer through the first dielectric layer; forming a second dielectric layer on an upper surface of the first dielectric layer; selectively etching the first and second dielectric layers and the first polysilicon layer to form a resistor poly (RPOLY) lower electrode; forming a second polysilicon layer on an upper surface of a resultant material; and forming a gate poly (GPOLY) by selectively etching the second polysilicon layer.

Abstract: Field effect transistors having tapered gate electrodes include a body region of first conductivity type extending to a surface of a semiconductor substrate. Source and drain regions of second conductivity type are formed in the substrate and a gate electrode is formed on a portion of the surface extending opposite the body region and between the source and drain regions. A gate electrode insulating layer is also disposed between the gate electrode and the surface. To improve the transistor's withstand voltage capability by reducing field crowding, the gate electrode insulating layer is preferably formed to have a tapered thickness which increases in a direction from the source region to the drain region, and to reduce on-state resistance the drain region is formed in a self-aligned manner to the gate electrode.

Abstract: A method of forming an integrated circuit device includes the steps of forming a first insulating layer on an integrated circuit substrate, forming a first capacitor electrode on the insulating layer opposite the substrate, and forming a second insulating layer on the first capacitor electrode and on the insulating layer opposite the substrate. A contact hole is formed in the second insulating layer thus exposing a surface of the first capacitor electrode. In particular, the contact hole exposes an edge portion of the first capacitor electrode and extends beyond the edge portion of the first capacitor electrode. A capacitor dielectric layer is formed on the exposed portion of the first capacitor electrode wherein the capacitor dielectric layer extends beyond the edge portion of the first capacitor electrode. A second capacitor electrode is formed on the dielectric layer wherein the second capacitor electrode extends beyond the edge portion of the first capacitor electrode.

Abstract: A method of forming an integrated circuit device includes the steps of forming a first insulating layer on an integrated circuit substrate, forming a first capacitor electrode on the insulating layer opposite the substrate, and forming a second insulating layer on the first capacitor electrode and on the insulating layer opposite the substrate. A contact hole is formed in the second insulating layer thus exposing a surface of the first capacitor electrode. In particular, the contact hole exposes an edge portion of the first capacitor electrode and extends beyond the edge portion of the first capacitor electrode. A capacitor dielectric layer is formed on the exposed portion of the first capacitor electrode wherein the capacitor dielectric layer extends beyond the edge portion of the first capacitor electrode. A second capacitor electrode is formed on the dielectric layer wherein the second capacitor electrode extends beyond the edge portion of the first capacitor electrode.