Abstract: An error correction method and apparatus for correcting multiple errors in received digital data word signals calculates syndromes S.sub.0, S.sub.1, S.sub.2 and S.sub.3 from a block of n received data words and a parity check matrix H. First coefficients .sigma..sub.1 and .sigma..sub.2 are calculated from the derived syndromes and a second coefficient K is calculated from the first coefficients .sigma..sub.1 and .sigma..sub.2. An error location value x.sub.1 is calculated from the second coefficient K, actual error location values X.sub.1 and X.sub.2 are calculated from the value x.sub.1, and error values Y.sub.1 and Y.sub.2 are calculated from the actual error location values X.sub.1 and X.sub.2. The received data words are then corrected by applying the calculated error values Y.sub.1 and Y.sub.2. The error location value x.sub.1 calculator is preferably constituted by logic gates which enable the apparatus to be smaller and faster than those using a conventional ROM table.

Abstract: An operation method and apparatus over Galois Field GF(2.sup.m) using a subfield GF(2.sup.m/2). The operation apparatus includes a conversion circuit for converting the elements represented by a basis of GF(2.sup.m) into the elements represented by a basis of GF(2.sup.m/2); an operation circuit for performing an operation over GF(2.sup.m/2) with respect to the elements represented by the basis of GF(2.sup.m/2); and a reversion circuit for reverting the operated elements represented by the basis of GF(2.sup.m/2) to the elements represented by the basis of GF(2.sup.m), thereby performing high speed operation and simplifying circuit construction.

Abstract: This invention presents improved epoxy-based die attach adhesives which are of low viscosity, high ionic purity, and stable toward thermal cycling. This improvement is obtained by including in the formulation carboxy terminated polymers which are the reaction products of polyether diols with cyclic dianhydrides.

Abstract: A borderless master slice semiconductor device is disclosed which comprises a plurality of first conduction type well regions arranged in a matrix type on the whole face of a second conduction type wafer; a plurality of second conduction type MOS transistor groups; a plurality of first conduction type diffusion regions arranged alterntely with the said second conduction type MOS transistor groups on the same row; a plurality of first conduction type MOS transistor groups arranged in a row direction facing opposingly with said second conduction type MOS transistor groups; and a plurality of second conduction type diffusion regions arranged alternately with said first conduction type MOS transistor groups on the same row. The device of the present invention thus constituted will bring the result that the master chip can be designed arbitrarily upon to the optimum size correspondingly with customer's order and that the production process can be singularized and the product control can be simplified.