Abstract: The present invention is to provide an image sensor, including: a semiconductor substrate of a first conductive type: a peripheral circuit formed on a first region of the semiconductor substrate, wherein a ground voltage level is applied to the first region; a unit pixel array having a plurality of unit pixels formed on a second region of the semiconductor substrate, wherein the first region is isolated from the second region and wherein a negative voltage level is applied to the second region; and a negative voltage generator for providing the negative voltage for the second region.

Abstract: The present invention is to provide an image sensor, including: a semiconductor substrate of a first conductive type: a peripheral circuit formed on a first region of the semiconductor substrate, wherein a ground voltage level is applied to the first region; a unit pixel array having a plurality of unit pixels formed on a second region of the semiconductor substrate, wherein the first region is isolated from the second region and wherein a negative voltage level is applied to the second region; and a negative voltage generator for providing the negative voltage for the second region.

Abstract: A method for fabricating a metal oxide semiconductor field effect transistor wherein source/drain junctions are formed by depositing and etching an oxide film having a desired thickness prior to the formation of a pocket region carried out by a pocket ion implantation after forming a gate oxide film and gate electrode on a channel region formed by implanting impurity ions in a silicon substrate. The pocket region is formed by impurity ions in source/drain regions exposed by etching the oxide film. Accordingly, it is possible to reduce the thermal budget applied to the source/drain junctions. As a result, the lateral diffusion of the impurity ions implanted in the source/drain junctions can be suppressed as much as possible. That is, the transistor fabricated in accordance with the present invention has a channel length longer than that obtained in accordance with the prior art. Accordingly, the transistor can have a highly compact or densely integrated size.

Abstract: A DRAM with reduced leakage current includes at least two line driving means for transmitting high potential to a line selected by an address signal externally input; a main power line for transmitting a power source voltage externally supplied; secondary power lines for transmitting the power source voltage to the respective line driving means; switching means respectively connected between the main power line and secondary power lines; block selection means for outputting a signal where two block selection addresses are logically combined, to each of the line driving means, in order to select and operate one of the line driving means; and switching control means for outputting a signal which controls each of the switching means through the logical combination of the output signal of the block selection means and a refresh operation mode signal.

Abstract: Row/column decoder circuits for a semiconductor memory device. Switching elements are used to separate a main power line from the row decoder circuit to block power from the main power line to the row decoder circuit when a word line is not driven. Therefore, the amount of standby current consumption can be reduced. Also, switching elements are used to separate a main power line from the column decoder circuit to block power from the main power line to the column decoder circuit when a bit line is not selected. Therefore, the amount of standby current consumption can be reduced.

Abstract: In the manufacturing process of a Dynamic Random Access Memory cell, the conducting layer used for preventing the capacitive coupling between a bit line and a word line is formed over the surface of the entire memory cell excepting the contact region of a bit line and a storage electrode. Moreover, as the conducting layer used for preventing the capacitive coupling is used as an etching barrier in the etching process forming a contact hole, self-aligned contacts are formed. Therefore, the operation of the unwanted cell of a Dynamic Random Access Memory cell caused by the capacitive coupling is protected and a highly integrated Dynamic Random Access Memory cell is manufactured.

Abstract: In the manufacturing process of a Dynamic Random Access Memory cell, the conducting layer used for preventing the capacitive coupling between a bit line and a word line is formed over the surface of the entire memory cell excepting the contact legion of a bit line and a storage electrode. Moreover, as the conducting layer used for preventing the capacitive coupling is used as an etching barrier in the etching process forming a contact hole, self-aligned contacts are formed. Therefore, the operation of the unwanted cell of a Dynamic Random Access Memory cell caused by the capacitive coupling is protected and a highly integrated Dynamic Random Access Memory cell is manufactured.