Abstract: A memory test device for testing a memory device is provided. The memory test device includes a sequencer configured to output first and second sequencer outputs that are different from each other in response to a sequencer input. A first pattern generator is configured to output a first test pattern according to the first sequencer output. A second pattern generator is configured to output a second test pattern according to the second sequencer output. A selector is coupled to the first and second pattern generators and configured to output write data according to the first test pattern and the second test pattern.

Abstract: A semiconductor test system includes a user device configured to operate a reference device in accordance with an interface signal based on a timing signal having a variable operating frequency, a pattern synthesis apparatus configured to measure an interval between adjacent edges of the timing signal transmitted from the user device, and extract a logic value of the interface signal in accordance with the timing signal so as to generate test pattern data, and a test device configured to receive the test pattern data, reconstruct the timing signal based on the measured interval, generate a test driving signal such that the logic value is extracted from a device under test (DUT) based on the reconstructed timing signal, and apply the test driving signal to the DUT so as to determine an operating state of the DUT.

Abstract: A memory test device for testing a memory device is provided. The memory test device includes a sequencer configured to output first and second sequencer outputs that are different from each other in response to a sequencer input. A first pattern generator is configured to output a first test pattern according to the first sequencer output. A second pattern generator is configured to output a second test pattern according to the second sequencer output. A selector is coupled to the first and second pattern generators and configured to output write data according to the first test pattern and the second test pattern.

Abstract: A signal capture system for capturing a signal and storing the captured signal in a storage apparatus in real time, and a test apparatus including the signal capture system. The signal capture system includes a printed circuit board; a socket that is connected to the printed circuit board and on which a reference memory component is mounted; and an interposer that is mounted on the printed circuit board, is connected to the socket, an external apparatus, and a storage apparatus, receives first signals from the reference memory component and transmits the received first signals to the external apparatus and the storage apparatus, and receives second signals from the external apparatus and transmits the received second signals to the reference memory component and the storage apparatus, wherein a shape of the socket is defined according to a type of the reference memory component.

Abstract: A semiconductor test system includes a user device configured to operate a reference device in accordance with an interface signal based on a timing signal having a variable operating frequency, a pattern synthesis apparatus configured to measure an interval between adjacent edges of the timing signal transmitted from the user device, and extract a logic value of the interface signal in accordance with the timing signal so as to generate test pattern data, and a test device configured to receive the test pattern data, reconstruct the timing signal based on the measured interval, generate a test driving signal such that the logic value is extracted from a device under test (DUT) based on the reconstructed timing signal, and apply the test driving signal to the DUT so as to determine an operating state of the DUT.

Abstract: A field mounting-type test apparatus and method for enhancing competitiveness of a product by simulating various test conditions including a mounting environment for improving quality reliability of a memory device and by minimizing overall loss due to change in a mounting environment thus reducing testing time and cost. The field mounting-type test apparatus includes a mass storage device configured to store logic data simulating a mounting environment of a device under test (DUT) and a tester main frame configured to test the DUT using the logic data.

Abstract: A signal capture system for capturing a signal and storing the captured signal in a storage apparatus in real time, and a test apparatus including the signal capture system. The signal capture system includes a printed circuit board; a socket that is connected to the printed circuit board and on which a reference memory component is mounted; and an interposer that is mounted on the printed circuit board, is connected to the socket, an external apparatus, and a storage apparatus, receives first signals from the reference memory component and transmits the received first signals to the external apparatus and the storage apparatus, and receives second signals from the external apparatus and transmits the received second signals to the reference memory component and the storage apparatus, wherein a shape of the socket is defined according to a type of the reference memory component.

Abstract: Provided are a field mounting-type test apparatus and method, which can enhance competitiveness of a product by simulating various test conditions including a mounting environment so as to improve quality reliability of a memory device and by minimizing overall loss due to change in a mounting environment so as to reduce testing time and cost. In accordance with example embodiments, the field mounting-type test apparatus may include a mass storage device configured to store logic data simulating a mounting environment of a device under test (DUT) and a tester main frame configured to test the DUT by using the logic data.

Abstract: A method of generating pulses includes setting a cycle based on a frequency of reference clock, determining a total number of the pulses to be generated during the cycle, calculating the number of one or more first reference clocks used to determine a width of one or more first pulses, the number of one or more second reference clocks used to determine a width of one or more second pulses, a first pulse number for the first pulses and a second pulse number for the second pulses on the basis of the cycle and the total number of the pulses, and generating the first pulse number of the first pulse and the second pulse number of the second pulses during the cycle. A motor control system employs the above pulse generating method and a pulse generator using the method to improve accuracy of controllability of a motor by generating the total number of the pulses during a cycle, and decrease a manufacturing cost.

Abstract: A method of generating pulses includes setting a cycle based on a frequency of reference clock, determining a total number of the pulses to be generated during the cycle, calculating the number of one or more first reference clocks used to determine a width of one or more first pulses, the number of one or more second reference clocks used to determine a width of one or more second pulses, a first pulse number for the first pulses and a second pulse number for the second pulses on the basis of the cycle and the total number of the pulses, and generating the first pulse number of the first pulse and the second pulse number of the second pulses during the cycle. A motor control system employs the above pulse generating method and a pulse generator using the method to improve accuracy of controllability of a motor by generating the total number of the pulses during a cycle, and decrease a manufacturing cost.

Abstract: An interrupt processing apparatus is disclosed. The apparatus processes interrupts from a plurality of interrupt sources by a central processing unit having one or more input ports. The apparatus has an interrupt controller for outputting an interrupt request signal for requesting an interrupt process from a corresponding interrupt source to a designated input port if the central processing unit assigns a priority to the corresponding interrupt source which generates the interrupt such that the apparatus processes interrupts from the interrupt sources more than the number of the input ports. The interrupt controller has a detection unit and a signal generating unit for outputting the interrupt request signal to a designated input port in conjunction with an operation of the detection unit.

Abstract: An apparatus for eliminating variable offset values of current detecting signals and its method having a current detector for detecting feedback current from a three-phase AC motor and for converting the feedback current into voltage detecting signals containing offset elements, differential amplifiers for differentially operating a feedback analog offset signal and the voltage detecting signals, output amplifiers for amplifying the differentially operated voltage detecting signals to fit within the input range for controlling, an analog/digital converter for converting the amplified signals into digital signals, a control part for adding up the digital signals to a digital offset value and for comparing the digital offset value with a predetermined offset command and for applying a proportional plus integral function to the compared result and for outputting a digital offset signal of a pulse-width modulation waveform, and a digital/analog converter for converting the digital offset signal into the analog of