Abstract: A solid state drive apparatus includes a case including a base and side walls extending upward along a circumference of the base, an electrostatic prevention structure of a metal pillar spaced apart from the side walls and protruding from at least a partial surface of the base and an electrostatic absorbing member on at least a partial surface of the metal pillar, a package substrate module mounted on the electrostatic prevention structure in the case, and a cover covering the case and the package substrate module.

Abstract: An apparatus and method for manufacturing a grilled seaweed includes the apparatus comprising a grilling unit having a first housing with a first inlet opening and a first outlet opening which communicate with each other; a first conveyor for transferring a sheet of seaweed from the first inlet opening to the first outlet opening; a first heating source installed over the first conveyor to discharge a flame onto a top surface of the seaweed being transferred by the first conveyor; and a second heating source installed on both sides of a lower portion of the first conveyor to apply a flame onto a bottom surface of the seaweed being transferred by the first conveyor.

Abstract: Provided are a separator coating composition for a secondary battery including inorganic particles and a silane salt compound having a specific structure, a separator using the same, and an electrochemical device including the same. Specifically, a separator coating composition for a secondary battery which implements adhesion between an inorganic material layer and a porous substrate without including an acid/polymer-based organic binder in a coating composition for forming the inorganic material layer on one or both surfaces of the porous substrate and does not need a separate dispersing agent for dispersing the inorganic particles, a separator manufactured using the same, and an electrochemical device including the separator are provided.

Abstract: A solid state drive apparatus includes a case including a base and side walls extending upward along a circumference of the base, an electrostatic prevention structure of a metal pillar spaced apart from the side walls and protruding from at least a partial surface of the base and an electrostatic absorbing member on at least a partial surface of the metal pillar, a package substrate module mounted on the electrostatic prevention structure in the case, and a cover covering the case and the package substrate module.

Abstract: A solid state drive apparatus includes a case including a base and side walls extending upward along a circumference of the base, an electrostatic prevention structure of a metal pillar spaced apart from the side walls and protruding from at least a partial surface of the base and an electrostatic absorbing member on at least a partial surface of the metal pillar, a package substrate module mounted on the electrostatic prevention structure in the case, and a cover covering the case and the package substrate module.

Abstract: A method for fabricating a semiconductor device includes: forming a dielectric layer over a substrate; forming a hole-shaped partial via in the dielectric layer; forming a line-shaped trench that partially overlaps with the partial via and has a greater line width than a line width of the partial via in the dielectric layer; forming a hole-shaped via that has a smaller line width than the line width of the partial via and penetrates the dielectric layer on a lower surface of the partial via; and gap-filling the via, the partial via and the trench with a conductive material, wherein a lower surface of the trench is positioned at a higher level than the lower surface of the partial via.

Abstract: A semiconductor memory device includes a memory region from which first data and second data are sequentially read, and a data output circuit suitable for selectively performing a reset operation on a data pad according to a logical relationship between the first and second data during an output disable period between a first output enable period corresponding to first output data and a second output enable period corresponding to second output data, when sequentially outputting the first and second output data corresponding to the first and second data through the data pad.

Abstract: Disclosed is a method of quantifying furan concentration to efficiently manage a deterioration state of a transformer in the field. The method of quantifying furan concentration includes: measuring a color-development degree of an extraction solution by making the extraction solution containing furan extracted from an insulating-oil sample mix and react with a color reagent; and quantifying furan concentration by correction based on a correlation between a precise analysis and a simple analysis with regard to the color-development degree of the extraction solution, wherein the precise analysis is to obtain a quantitative value through color column separation based on high performance liquid chromatography (HPLC) in a laboratory to analyze a furan compound in insulating oil of a transformer, and the simple analysis is to obtain a chromaticity value in a field with regard to actual transformer samples.

Abstract: An optical system is provided which includes a light source which outputs light; a first waveguide; a transmissive reflective layer provided on a top surface of the first waveguide and configured to reflect some light and transmit the remaining light incident thereon; a second waveguide provided on a top surface of the transmissive reflective layer; an in-coupler provided on the first waveguide and configured to allow the light output by the light source to enter the first waveguide; and an out-coupler provided on one of the first waveguide and the second waveguide and configured to emit light from the optical system.

Abstract: Provided is a memory device. The memory device includes a module board on which one or more semiconductor devices are disposed and a conductive plate mounted on a first side of the module board. The conductive plate includes a shielding region and a non-shielding region. A pad is disposed in the shielding region of the conductive plate.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: Provided is a virtual image display device including: an image generator outputting a virtual image; a filter transmitting light in a first polarization state in the output virtual image; a multipath optical element guiding the transmitted light in the first polarization state; a first optical element arranged on a first side of the multipath optical element and allowing the guided light in the first polarization state and real-world light to pass therethrough; a second optical element arranged on a second side opposite to the first side of the multipath optical element and allowing the real-world light to pass therethrough; and a processor controlling the image generator, the first optical element, and the second optical element.

Abstract: A semiconductor device includes a phase control signal generation circuit, a phase detection circuit, and a selection/transmission circuit. The phase control signal generation circuit outputs one of a command-shifted signal generated from a command/address signal and a clock-shifted signal generated from a clock signal as a phase control signal, based on a leveling enablement signal. The phase detection circuit detects a phase of a leveling clock signal in synchronization with the phase control signal to generate a detection signal. The selection/transmission circuit outputs the detection signal as one of a phase detection signal and a phase adjustment signal based on the leveling enablement signal.

Abstract: A semiconductor device includes a phase control signal generation circuit, a phase detection circuit, and a selection/transmission circuit. The phase control signal generation circuit outputs one of a command-shifted signal generated from a command/address signal and a clock-shifted signal generated from a clock signal as a phase control signal, based on a leveling enablement signal. The phase detection circuit detects a phase of a leveling clock signal in synchronization with the phase control signal to generate a detection signal. The selection/transmission circuit outputs the detection signal as one of a phase detection signal and a phase adjustment signal based on the leveling enablement signal.

Abstract: A hub apparatus and a method are provided for selecting a device. The method includes receiving a service request; determining a sensor based on the received service request; receiving state information from a device including the determined sensor; and selecting the device based on the received state information.

Abstract: A semiconductor device includes a transmission circuit coupled between a first voltage supply node and a second voltage supply node, and suitable for outputting an output data signal corresponding to a data value to an output terminal during a data output enable period, and a switching circuit coupled between the first and second voltage supply nodes, and suitable for providing a current path between the first and second voltage supply nodes during a data output disable period.

Abstract: A semiconductor device includes a phase difference detection circuit and an internal circuit. The phase difference detection circuit generates first and second phase difference detection signals by comparing a phase of a phase detection clock signal, generated from a command/address signal in synchronization with a clock signal, with phases of a division clock signal and an internal division clock signal that are generated by dividing a frequency of a data clock signal according to an operation mode. The internal circuit recognizes the phases of the division clock signal and the internal division clock signal according to a logic level combination of the first and second phase difference detection signals.

Abstract: A memory system comprises: a memory cell array suitable for storing first data and a first parity, which is used to correct an error of the first data; and an error correcting circuit suitable for generating second data and a second parity, which includes bits obtained by correcting an error of the first parity and a bit obtained by correcting an error of a second sub-parity; wherein the error correcting circuit includes: a single error correction and double error detection (SECDED) parity generator suitable for generating a second pre-parity, which includes a first sub-parity and the second sub-parity; a syndrome decoder suitable for generating a first parity error flag and a first data error flag by decoding a syndrome; a SEC parity corrector suitable for correcting an error of the first parity based on the first parity error flag; a DED parity error detector suitable for generating a second sub-parity error flag based on an error information of the first data used to generate the second sub-parity; and a D