Abstract: A glass stack structure includes: a carrier plate having a width in a first direction and a length in a second direction; a stack glass on the carrier plate and including mother glasses sequentially stacked therein; adhesive lines including a high viscous material and arranged at peripheral portions of the carrier plate and the mother glasses to adhere the carrier plate to the mother glasses, and the adhesive lines includes wave lines extending in the second direction and spaced apart from each other in the first direction and linear lines extending in the first direction and spaced apart from each other in the second direction; and an adhesive layer including a low viscous material and covering a cell area of the carrier plate and the mother glasses to adhere the carrier plate to the mother glasses, where the cell area is defined by the wave lines and the linear lines.

Abstract: A memory device includes a memory cell array formed in a semiconductor die, the memory cell array including a plurality of memory cells to store data and a calculation circuit formed in the semiconductor die. The calculation circuit performs calculations based on broadcast data and internal data and omits the calculations with respect to invalid data and performs the calculations with respect to valid data based on index data in a skip calculation mode, where the broadcast data are provided from outside the semiconductor die, the internal data are read from the memory cell array, and the index data indicates whether the internal data are the valid data or the invalid data. Power consumption is reduced by omitting the calculations and the read operation with respect to the invalid data through the skip calculation mode based on the index data.

Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.

Abstract: A method for testing an IT system automatically, when it comes to testing based on real transaction data including: (a) obtaining a transaction message by capturing a network packet transmitted and received between a user system and a transaction processing system; (b) transmitting a request data included in the transaction message to the system under test; (c) receiving a response data from the system under test; and (d) comparing the response data received from the system under test and a response data included in the transaction message and determining success or failure, is provided.

Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.

Abstract: A phase change memory system comprises a phase change memory device which includes a plurality of memory units including a plurality of memory cells in units of at least one or more codewords and a phase change memory controller which performs a chip refresh operation for refreshing the entire phase change memory device, wherein the phase change memory device includes a setting circuitry which determines one of the plurality of memory units in a desired manner, a refresh controller which refreshes the decided memory unit, a sensing circuitry which senses data of at least one or more codewords included in the refreshed memory unit, and a request circuitry which requests a host for the chip refresh operation on the basis of a result of the sensing operation.

Abstract: A semi-pneumatic tire includes a tread portion configured to make contact with a road surface, a non-pneumatic portion coupled to an inner circumferential surface of the tread portion. The semi-pneumatic tire further includes a pneumatic portion coupled to an inner circumferential surface of the non-pneumatic portion and provided with a space into which an air is filled, and bonding layers respectively interposed between the tread portion and the non-pneumatic portion and between the non-pneumatic portion and the pneumatic portion. The non-pneumatic portion includes a band portion including an inner band coupled to an outer circumferential surface of the pneumatic portion and an outer band spaced apart from the inner band and surrounding an outer circumferential surface of the inner band, and spokes provided between the inner band and the outer band to connect the inner band and the outer band.

Abstract: According to an exemplary embodiment, a memory device may include a memory cell array that includes memory cells connected to word lines arranged in sequential order depending on a sequential change of a row address, a row decoder that, for each row address input to the row decoder, scrambles a first bit of the row address and a second bit of the row address depending on a selection signal, thereby forming a scrambled row address, decodes the scrambled row address, and selects a word line from the word lines based on the scrambled row address, and an anti-fuse array that includes an anti-fuse in which a logical value of the selection signal is programmed. A first word line and a second word line of the word lines may be adjacent to each other, and a difference between a first value of the row address corresponding to the first word line and a second value of the row address corresponding to the second word line may be a value corresponding to the first bit.

Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.

Abstract: Disclosed is a micro light emitting diode (LED) display device which is capable of implementing a full color of high resolution, the micro LED display device including: a micro LED driving substrate (backplane) in which a plurality of CMOS cells is arranged in rows and columns; and a micro LED panel which is flip-chip bonded onto the micro LED driving substrate, and includes a plurality of micro LED pixels electrically connected with the plurality of CMOS cells, in which the micro LED panel includes the plurality of micro LED pixels formed by etching a first surface of an emission structure along a unit pixel region, and a plurality of separators formed on a second surface of the emission structure corresponding to positions of portions formed by etching the emission structure in a vertical direction.

Abstract: Provided is a Maxwellian view display which uses a space-time multiplexing scheme and widens a field of view, thereby having a degree of freedom within a set area instead of a fixed position while maintaining the advantage of the existing Maxwellian view, in which a clear image can be observed irrespective of the difference in individual ability for focal point adjustment since the focal point does not need to be adjusted. According to an embodiment of the present invention, a display includes: a light source unit for changing the position of a point light source according to time; a first lens for converting the light emitted from the light source unit to be parallel; an image generating unit for generating an image using the parallel light incident from the first lens; and a second lens for focusing the image generated by the image generating unit.

Abstract: The present invention relates to a puzzle-type micro light emitting diode (LED) display device which is capable of implementing a display having various sizes, the micro LED display device including: a micro LED panel in which a plurality of micro LED pixels is arranged in rows and columns; and a micro LED driving substrate (backplane) configured to include an active matrix (AM) circuit unit including a plurality of CMOS cells corresponding to the plurality of micro LED pixels, and a control circuit unit disposed in an outer region of the AM circuit unit, in which the control circuit unit is disposed to be adjacent to two sides among four sides of the micro LED panel.

Abstract: Disclosed are a functional image tile and a manufacturing method therefor, the tile: being manufactured by printing a desired image on a surface of a tile manufactured through a mixture produced by mixing red clay, basalt fiber and mulberry fiber with a raw material formed by mixing plaster and water; being capable of smoothly absorbing ink during image printing since the red clay and the plaster having excellent absorbency are mixed; enabling the image printed on the surface thereof to be prevented from peeling off or spreading by moisture; and exhibiting excellent heat resistance, strength, and moisture-adjusting capability since the basalt fiber and the mulberry fiber are mixed together.

Abstract: Disclosed is a micro light emitting diode (LED) display device which is capable of implementing a full color of high resolution, the micro LED display device including: a micro LED driving substrate (backplane) in which a plurality of CMOS cells is arranged in rows and columns; and a micro LED panel which is flip-chip bonded onto the micro LED driving substrate, and includes a plurality of micro LED pixels electrically connected with the plurality of CMOS cells, in which the micro LED panel includes the plurality of micro LED pixels formed by etching a first surface of an emission structure along a unit pixel region, and a plurality of separators formed on a second surface of the emission structure corresponding to positions of portions formed by etching the emission structure in a vertical direction.

Abstract: An apparatus for performing a wafer spin process is provided. The apparatus includes a base member, a rotatable member, and a wafer guide. The base member includes a plurality of first magnetic components. The rotatable member is disposed over the base member and includes a plurality of second magnetic components. The wafer guide is disposed over the rotatable member for holding a wafer.

Abstract: According to an embodiment of the present invention, a method for testing an IT system automatically, when it comes to testing based on real transaction data, comprising: (a) obtaining a transaction message by capturing a network packet transmitted and received between a user system and a transaction processing system; (b) transmitting a request data included in the transaction message to the system under test; (c) receiving a response data from the system under test; and (d) comparing the response data received from the system under test and a response data included in the transaction message and determining success or failure, is provided.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a calculation circuit configured to perform a calculation on information bits and weight bits based on a calculation window having a first size, the information bits and weight bits being included in a user data set, the memory cell array being configured to store the user data set, the calculation circuit being further configured to receive the user data set through the page buffer circuit; and a data input/output (I/O) circuit connected to the calculation circuit, wherein the calculation circuit is further configured to provide an output data set to the data I/O circuit in response to the calculation circuit completing the calculation with respect to all of the information bits and the weight bits, and wherein the output data set corresponds to a result of the completed calculation.

Abstract: A method for diagnosing lung cancer in a subject by using a complex biomarker group is provided. The method includes steps of: (a) a computing system (1) acquiring a model M by using expression level data by individual biomarkers in the complex biomarker group and then (2) acquiring expression level data by the individual biomarkers measured from a biological specimen of the subject or their processed data Bk; and (b) the computing system determining whether lung cancer is detected in the subject by using the acquired data of the subject by referring to the model M; wherein the complex biomarker group includes CEA, HE4, ApoA2, TTR, sVCAM-1 and RANTES.

Abstract: In view of the above, the disclosure provides a non-pneumatic tire capable of enhancing a load supporting performance and a shock absorbing effect and improving a braking and traction performance. The present disclosure provides a non-pneumatic tire comprising a band part and a spoke part; where, a band part includes an inner band and an outer band that is separated from the inner band and surrounds an outer peripheral surface of the inner band; and where, a spoke part includes a plurality of first spokes that is arranged in a circumferential direction between the inner band and the outer band and connects the inner band and the outer band. Furthermore, according to another embodiment, a spoke part may include second spokes that connected to first spokes adjacent to each other at wherein first embodiment.

Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.