Patents by Inventor In-Tack Han

In-Tack Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cell scheduling method of input and output buffered switch using simple iterative matching algorithm
    Patent number: 6904047
    Abstract: A method for scheduling an input and output buffered ATM or packet switch and, more particularly, to a method for cell-scheduling an input and output buffered switch that is adapted to a high-speed large switch is provided. The input and output buffered switch has multiple switching planes, and its structure is used to compensated for decreasing performance of the input buffered switch resulting from HOL (head-of-line) blocking of the input buffered switch. The input and output buffered switch consists of input buffer modules grouping several input ports and output ports and output buffer modules, and each input buffer module has several FIFO queues for the associated module output buffer modules. In the input and output buffered switch having multiple switching planes, cell scheduling is carried out using a simple iterative matching (SIM) method.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: June 7, 2005
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Man-Soo Han, Jung-Hee Lee, In-Tack Han, Bhum-Cheol Lee
  • Cell scheduling method of input and output buffered switch using simple iterative matching algorithm
    Publication number: 20010043606
    Abstract: A method for scheduling an input and output buffered ATM or packet switch and, more particularly, to a method for cell-scheduling an input and output buffered switch that is adapted to a high-speed large switch is provided. The input and output buffered switch has multiple switching planes, and its structure is used to compensated for decreasing performance of the input buffered switch resulting from HOL (head-of-line) blocking of the input buffered switch. The input and output buffered switch consists of input buffer modules grouping several input ports and output ports and output buffer modules, and each input buffer module has several FIFO queues for the associated module output buffer modules. In the input and output buffered switch having multiple switching planes, cell scheduling is carried out using a simple iterative matching (SIM) method.
    Type: Application
    Filed: May 17, 2001
    Publication date: November 22, 2001
    Inventors: Man-Soo Han, Jung-Hee Lee, In-Tack Han, Bhum-Cheol Lee