Patents by Inventor In-won O
In-won O has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11930652Abstract: An organic light emitting display apparatus including a substrate including a plurality of pixel areas; a pixel electrode on the substrate; an opposite electrode on the pixel electrode, the opposite electrode transmitting light; an organic light emitting layer between the pixel electrode and the opposite electrode, the organic light emitting layer emitting a first light toward the opposite electrode; a light emitting layer on the opposite electrode, the light emitting layer absorbing a portion of the first light and emitting a second light; and a sealing layer on the light emitting layer, the sealing layer sealing the pixel electrode, the opposite electrode, the organic light emitting layer, and the light emitting layer.Type: GrantFiled: December 12, 2022Date of Patent: March 12, 2024Assignee: Samsung Display Co., Ltd.Inventors: Chi-O Cho, Byungchoon Yang, Young-Jun Seo, Won Sang Park
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Publication number: 20230047026Abstract: A semiconductor package includes: a first wiring structure including a first wiring layer, and a second wiring layer disposed on the first wiring layer, and connected to a first connecting structure placed disposed on the first wiring layer; a first semiconductor chip disposed on the first wiring structure and connected to the first wiring structure through a first connecting pad disposed on a first side of the first semiconductor chip; a second wiring structure disposed on the first semiconductor chip; and an insulating member disposed between the first and second wiring structures, wherein the first wiring structure further includes a first signal pattern that is electrically connected to the first connecting pad, and the first signal pattern redistributes the first connecting pad to the first connecting structure via the insulating member.Type: ApplicationFiled: July 19, 2022Publication date: February 16, 2023Inventors: Seung Soo HA, Ju-Youn CHOI, In Won O, Jun Ho LEE
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Patent number: 11166368Abstract: A printed circuit board that includes a base layer having a first surface and a second surface opposing each other. A first structure is disposed on the first surface of the base layer. The first structure includes a first plate structure. A first connection structure is disposed on a same plane as the first plate structure and is spaced apart from the first plate structure. The first plate structure includes first openings. At least some of the first openings are linear openings having a line shape.Type: GrantFiled: February 11, 2020Date of Patent: November 2, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Ho Park, In Won O, Hak Jun Kim
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Publication number: 20200260577Abstract: A printed circuit board that includes a base layer having a first surface and a second surface opposing each other. A first structure is disposed on the first surface of the base layer. The first structure includes a first plate structure. A first connection structure is disposed on a same plane as the first plate structure and is spaced apart from the first plate structure. The first plate structure includes first openings. At least some of the first openings are linear openings having a line shape.Type: ApplicationFiled: February 11, 2020Publication date: August 13, 2020Inventors: Jung Ho PARK, In Won O, Hak Jun KIM
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Patent number: 9542978Abstract: A semiconductor package includes: a plurality of memory packages which are arranged on a substrate; and a logic chip, which has a rhombus shape including first through fourth corners and first through fourth sides connecting the first through fourth corners, is arranged adjacent to the plurality of memory packages, and includes a plurality of terminals that are electrically connected to the plurality of memory packages, as seen on a plan view of the semiconductor package, wherein the plurality of terminals include system address terminals which are adjacent to the first corner of the logic chip and first and second system data terminals which are respectively arranged on the first and second sides contacting the first corner. Another semiconductor package and a method of fabrication are disclosed.Type: GrantFiled: June 2, 2015Date of Patent: January 10, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-won Lee, Jang-mee Seo, In-won O
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Publication number: 20160049176Abstract: A semiconductor package includes: a plurality of memory packages which are arranged on a substrate; and a logic chip, which has a rhombus shape including first through fourth corners and first through fourth sides connecting the first through fourth corners, is arranged adjacent to the plurality of memory packages, and includes a plurality of terminals that are electrically connected to the plurality of memory packages, as seen on a plan view of the semiconductor package, wherein the plurality of terminals include system address terminals which are adjacent to the first corner of the logic chip and first and second system data terminals which are respectively arranged on the first and second sides contacting the first corner. Another semiconductor package and a method of fabrication are disclosed.Type: ApplicationFiled: June 2, 2015Publication date: February 18, 2016Inventors: Jong-won LEE, Jang-mee SEO, In-won O
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Patent number: 9059067Abstract: A semiconductor device includes an interposer mounting a semiconductor chip. The interposer includes a silicon substrate having a recessed region formed on a first surface, a first through via penetrating a first region of the silicon substrate from the first surface to an opposing second surface, an insulator disposed in the recessed region, and a first wire pattern at least partially disposed on the insulator and electrically connecting the first through via to the semiconductor chip.Type: GrantFiled: September 19, 2011Date of Patent: June 16, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-seok Choi, So-young Lim, In-won O
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Patent number: 8981514Abstract: A semiconductor package includes a light transmissive cover having a conductive pattern, a substrate having a cavity, a semiconductor chip in the cavity of the substrate and electrically connected to the conductive pattern arranged on the light transmissive cover, and a blocking pattern between the light transmissive cover and the substrate.Type: GrantFiled: September 12, 2012Date of Patent: March 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Han-Sung Ryu, Byoung-Rim Seo, In-Won O
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Patent number: 8823185Abstract: Provided is a semiconductor package including: a semiconductor chip mounted on a die pad; at least one lead connected electrically to the semiconductor chip; and a flexible film substrate including a metal wiring, which electrically connects the semiconductor chip and the at least one lead, wherein the semiconductor chip is electrically connected to the film substrate through a first connection member which contacts the semiconductor chip and the metal wiring; and the film substrate is electrically connected to the at least one lead through a second connection member which contacts the metal wiring and the at least one lead.Type: GrantFiled: September 24, 2011Date of Patent: September 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: In Won O, Woojae Kim, YoungHoon Ro, HanShin Youn, Yechung Chung, YunSeok Choi
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Publication number: 20130264703Abstract: A semiconductor package includes a holder covering or encapsulating an edge part of a semiconductor chip. Thus, it may be possible to isolate the edge part on which contaminants may easily exist from a pixel part. As a result, the contaminants from the edge part do not contaminate the pixel part, so that distortion of an image may be prevented.Type: ApplicationFiled: February 27, 2013Publication date: October 10, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yujung TAE, ByoungRim SEO, IN WON O
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Publication number: 20130181314Abstract: A semiconductor package includes a light transmissive cover having a conductive pattern, a substrate having a cavity, a semiconductor chip in the cavity of the substrate and electrically connected to the conductive pattern arranged on the light transmissive cover, and a blocking pattern between the light transmissive cover and the substrate.Type: ApplicationFiled: September 12, 2012Publication date: July 18, 2013Inventors: Han-Sung RYU, Byoung-Rim SEO, In-Won O
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Publication number: 20120168918Abstract: Provided is a semiconductor package including: a semiconductor chip mounted on a die pad; at least one lead connected electrically to the semiconductor chip; and a flexible film substrate including a metal wiring, which electrically connects the semiconductor chip and the at least one lead, wherein the semiconductor chip is electrically connected to the film substrate through a first connection member which contacts the semiconductor chip and the metal wiring; and the film substrate is electrically connected to the at least one lead through a second connection member which contacts the metal wiring and the at least one lead.Type: ApplicationFiled: September 24, 2011Publication date: July 5, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In Won O, Woojae KIM, YoungHoon RO, HanShin YOUN, Yechung CHUNG, YunSeok CHOI
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Publication number: 20120091468Abstract: A semiconductor device includes an interposer mounting a semiconductor chip.Type: ApplicationFiled: September 19, 2011Publication date: April 19, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun-seok Choi, So-young Lim, In-won O
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Patent number: D384344Type: GrantFiled: October 3, 1995Date of Patent: September 30, 1997Assignee: LG Electronics, Inc.Inventor: Won O Doo