Abstract: An embodiment vehicle body includes a front cross portion having a substantially uniform cross-section throughout its entire length, a rear cross portion spaced apart from the front cross portion, the rear cross portion having a substantially uniform cross-section throughout its entire length, and a connection structure connecting the front cross portion and the rear cross portion.

Abstract: A 3D memory device, the device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the memory controller circuit includes a row buffer, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.

Abstract: A connector position alignment assembly includes a first part and a second part coupled to each other through a connector and including a guide portion aligning a position of the connector. The guide portion is provided with a guide pin and a guide boss including portions protruding toward each other, and the guide pin and the guide boss respectively protrude further than the connector, in a direction in which the first part and the second part face each other, such that a portion of the guide pin is accommodated in the guide boss before the connectors are coupled to each other.

Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

Abstract: The present invention relates to a novel naphthyridinone derivative compound, a pharmaceutically acceptable salt thereof, a hydrate thereof, or a stereoisomer thereof, which are each relevant to a compound for inhibiting ENPP1, a composition for inhibiting ENPP1, and a method for inhibiting ENPP1.

Abstract: Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

Abstract: An ion-exchange resin module and a deionization apparatus using same are proposed. An ion-exchange resin module may have the inside filled with ion-exchange resin and may be configured to have a pressing plate such that fluid in the ion-exchange resin is discharged. Multiple ion-exchange resin modules may be installed by being stacked in an inner space defined inside a tank of the deionization apparatus. A discharge pipe which passes through the lower end of the tank and extends to the upper end thereof may be installed in the inner space, the discharge pipe being located in a through duct which passes through the centers of the ion-exchange resin modules.

Abstract: A light-emitting element transfer system includes raw film cutting device for forming a transfer member by cutting a raw film, a stretching device for stretching a transfer film with a plurality of light-emitting elements disposed thereon, a circuit board support member for supporting a circuit board and transport head for adsorbing the transfer member and transferring the light-emitting elements on the transfer film onto the circuit board by using the adsorbed transfer member.

Abstract: A refrigerator door includes a color module which displays various colors by using LEDs. Accordingly, when a consumer desires to change the color of the refrigerator door, the color of the refrigerator door can be changed to color desired by the consumer.

Abstract: A transistor may include a first insulating layer disposed on a substrate, a dummy layer disposed on the first insulating layer, a semiconductor layer disposed on the dummy layer, the semiconductor layer including a first area, a second area, and a channel area disposed between the first and second areas, a second insulating layer disposed on the semiconductor layer, a gate electrode overlapping the channel area with the second insulating interposed therebetween, a third insulating layer disposed over the gate electrode, a first electrode disposed on the third insulating layer, the first electrode being electrically connected to the first area, and a second electrode disposed on the third insulating layer spaced apart from the first electrode, the second electrode being electrically connected to the second area. The dummy layer may include indium oxide, and the semiconductor layer may include indium gallium zinc oxide.

Abstract: An operating method of a controller that controls a memory device, comprises: generating a data chunk including user data to be programmed in a page of the memory device and an internal parity generated by performing first ECC encoding on the user data, the internal parity being generated when a size of the user data is smaller than a size of a data area of the page, generating a page chunk including the data chunk, meta data of the user data and an external parity generated by performing second ECC encoding on the meta data and the data chunk, and controlling the memory device to program the page chunk into the page.

Abstract: An eco-friendly power source, such as a battery module provided for a transportation vehicle includes a first sub-module and a second sub-module disposed in a first direction, the first sub-module and the second sub-module respectively including a plurality of battery cells stacked in a second direction, which is perpendicular to the first direction, and a lower cover coupled to the first sub-module and the second sub-module. The first sub-module and the second sub-module are disposed to be rotationally symmetrical to each other about a central axis, which is perpendicular to both the first direction and the second direction.

Abstract: An eco-friendly power source such as a battery module is provided for a transportation vehicle, including: a first sub-module and a second sub-module respectively including a cell stack in which a plurality of battery cells are stacked; and a central wall disposed between the first sub-module and the second sub-module, wherein the central wall includes a first central wall facing the first sub-module and a second central wall facing the second sub-module, wherein the first central wall has a rotationary symmetrical shape of the second central wall around a first axis.

Abstract: A manufacturing method of a catalyst may modify a carbon layer structure by using various heat treatment gases such as inert gas (Ar), hydrogen, and carbon monoxide in a carbon layer manufacturing process, thereby optimizing the carbon layer structure according to the purpose of a metal without changing a size of the metal.

Abstract: A 3D memory device, the device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the memory controller circuit includes a row buffer, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.

Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Abstract: Provided is an organic light emitting device comprising a light emitting layer comprising an organic alloy of a compound of Chemical Formula 1 and a compound of Chemical Formula 2, the device having improved driving voltage, efficiency, and lifespan: where A is a benzene ring fused with the two adjacent rings, X1, X2 and X3 are each independently CH or N, provided that at least one of X1, X2 and X3 is N, Ar1-Ar5 are each independently a substituted or unsubstituted C6-60 aryl or a substituted or unsubstituted C2-60 heteroaryl containing at least one of N, O and S, and the other substituents are defined in the specification, provided that at least one of Ar4 and Ar5 is substituted with at least one deuterium, or at least one R2 is deuterium.

Abstract: A 3D device, the device including: at least one first level including logic circuits; at least one second level bonded to the first level, where the at least one second level includes a plurality of transistors; connectivity structures, where the connectivity structures include a plurality of transmission lines, where the plurality of transmission lines are designed to conduct radio frequencies (“RF”) signals, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions; and a plurality of vias disposed through the at least one second level, where at least a majority of the plurality of vias have a diameter of less than 5 micrometers.

Abstract: A transistor array substrate includes a substrate, an active layer disposed on the substrate and including a channel region, a source region and a drain region, a gate insulating layer disposed on a part of the active layer, a gate electrode overlapping the channel region of the active layer and included in an electrode conductive layer which is disposed on the gate insulating layer, a source electrode included in the electrode conductive layer and in contact with a part of the source region of the active layer, and a drain electrode included in the electrode conductive layer and in contact with a part of the drain region of the active layer. The active layer includes an oxide semiconductor including crystals and is disposed as an island shape excluding a hole in a plan view.

Abstract: Provided a semiconductor memory device. The semiconductor memory device includes a substrate, a gate electrode on the substrate, a bit line on the substrate, a cell semiconductor pattern on a side of the gate electrode and electrically connected to the bit line, a capacitor structure including a first electrode electrically connected to the cell semiconductor pattern, a second electrode on the first electrode, and a capacitor dielectric film between the first electrode and the second electrode, a bit line strapping line spaced apart from the bit line in the second direction, and electrically connected to the bit line, a bit line selection line between the bit line and the bit line strapping line, and a selection semiconductor pattern between the bit line and the bit line strapping line and electrically connected to all of the bit line, the bit line strapping line, and the bit line selection line.