Abstract: A semiconductor device includes: a command generation circuit configured to generate a write strobe signal; a pipe control circuit configured to generate first to fourth input control signals and first to fourth output control signals which are sequentially enabled, when first and second write command pulses are inputted, and generate first to fourth internal output control signals after a preset period; and an address processing circuit configured to latch an address inputted through a command address, when the write strobe signal and the first to fourth input control signals are inputted, generate a bank group address and a column address from the latched address, when the first to fourth output control signals are inputted, and generate the bank group address and the column address by inverting the latched address, when the first to fourth internal output control signals are inputted.

Abstract: A semiconductor device includes an internal clock generation circuit, a command generation circuit, and an address generation circuit. The internal clock generation circuit generates a command clock signal and an inverted command clock signal, wherein a cycle of the command clock signal and a cycle of the inverted command clock signal are determined by a mode. The command generation circuit generates a first command based on a first internal control signal and the command clock signal and generates a second command based on a second internal control signal and the inverted command clock signal. The address generation circuit generates a latch address based on the first internal control signal or a second internal control signal.

Abstract: A semiconductor device includes: a command generation circuit configured to generate a write strobe signal; a pipe control circuit configured to generate first to fourth input control signals and first to fourth output control signals which are sequentially enabled, when first and second write command pulses are inputted, and generate first to fourth internal output control signals after a preset period; and an address processing circuit configured to latch an address inputted through a command address, when the write strobe signal and the first to fourth input control signals are inputted, generate a bank group address and a column address from the latched address, when the first to fourth output control signals are inputted, and generate the bank group address and the column address by inverting the latched address, when the first to fourth internal output control signals are inputted.

Abstract: A semiconductor device includes a flag pipe, a pattern mode control circuit, and a data copy control circuit. The flag pipe is configured to latch a pattern mode flag, a first pattern control flag, a second pattern control flag, a data copy flag, and an enlargement data copy flag based on a pipe input control signal and output a delayed pattern mode flag, a first delayed pattern control flag, a second delayed pattern control flag, and a synthesis data copy flag based on a pipe output control signal. The pattern mode control circuit is configured to set a first data pattern or a second data pattern based on the delayed pattern mode flag, the first delayed pattern control flag, and the second delayed pattern control flag. The data copy control circuit is configured to copy data inputted through a first data pad onto a data path electrically connected to a second data pad based on the synthesis data copy flag.

Abstract: A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

Abstract: A method of manufacturing a radar transparent cover may include steps of: injection molding a first transparent cover; inserting into a mold the first transparent cover made by the step of injection molding the first transparent cover and then, double injection molding a color resin on a back surface of the first transparent cover; and inserting into a mold the injection molded article made by the step of double injection molding the color resin and then, double injection molding a second transparent cover on a front surface of the first transparent cover.

Abstract: A semiconductor device includes a plurality of main contact plugs and a plurality of dummy contact plugs which pass through an insulating layer on a substrate. A plurality of upper interconnections is on the insulating layer. The plurality of dummy contact plugs include a first dummy contact plug. The plurality of upper interconnections include a first upper interconnection overlapping the first dummy contact plug. A vertical central axis of the first dummy contact plug is located outside the first upper interconnection.

Abstract: A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

Abstract: A semiconductor device and command generation method, the semiconductor device includes a command recovery circuit configured to receive a command from a plurality of commands, to store a code signal which is generated by encoding the received command from the plurality of commands, depending on the received command, and generate a plurality of internal commands by decoding a command code signal which is generated from the code signal after shifting the received command depending on a shifting control signal; and a memory circuit configured to perform an internal operation depending on the plurality of internal commands.

Abstract: A control method of a rear wheel steering system prevents a sudden change in a rear wheel steering control amount when an error occurs in a wheel speed sensor. The control method detects an error in wheel speed sensors based on output values of the wheel speed sensors. A vehicle speed is estimated by using output values of remaining normal wheel speed sensors except for an output value of an abnormal wheel speed sensor where an error is detected, when an error in the wheel speed sensor is detected. Rear wheels are steered and controlled based on the estimated vehicle speed.

Abstract: A signal generation circuit generates a first synchronization signal by delaying a first input signal in synchronization with a first division clock signal, and generates a second synchronization signal by delaying a second input signal in synchronization with a second division clock signal. The signal generation circuit adjusts pulse widths of the first and second synchronization signals based on an on-control signal and an off-control signal. The signal generation circuit includes a retiming circuit configured to generate an output signal by retiming a preliminary output signal, generated from the first and second synchronization signals, based on the first and second division clock signals.

Abstract: A signal driver includes a first driver, a second driver, an on-timing control circuit, and an off-timing control circuit. The first driver is configured to generate a first driving pulse signal by inverting and driving an input pulse signal. The second driver is configured to generate a second driving pulse signal by inverting and driving the first driving pulse signal. The on-timing control circuit is configured to pull-up drive or pull-down drive the first driving pulse signal based on a first on-timing control signal, a second on-timing control signal, and the input pulse signal. The off-timing control circuit is configured to pull-up drive or pull-down drive the second driving pulse signal based on a first off-timing control signal, a second off-timing control signal, and the first driving pulse signal.

Abstract: A semiconductor device includes an internal clock generation circuit, a command generation circuit, and an address generation circuit. The internal clock generation circuit generates a command clock signal and an inverted command clock signal, wherein a cycle of the command clock signal and a cycle of the inverted command clock signal are determined by a mode. The command generation circuit generates a first command based on a first internal control signal and the command clock signal and generates a second command based on a second internal control signal and the inverted command clock signal. The address generation circuit generates a latch address based on the first internal control signal or a second internal control signal.

Abstract: A method including generating position information and time information of a handwriting inputted on a device; generating pixel values of an image capturing the handwriting; generating an image file for facilitating a sequential reproduction of the handwriting by storing the position information and the time information of the handwriting in a first field of the image file and storing the pixel values in a second field of the image file; and transmitting the generated image file to another device.

Abstract: A method and an apparatus for recognizing characters using an image are provided. A camera is activated according to a character recognition request and a preview mode is set for displaying an image photographed through the camera in real time. An auto focus of the camera is controlled and an image having a predetermined level of clarity is obtained for character recognition from the images obtained in the preview mode. The image for character recognition is character-recognition-processed so as to extract recognition result data. A final recognition character row is drawn that excludes non-character data from the recognition result data. A first word is combined including at least one character of the final recognition character row and a predetermined maximum number of characters. A dictionary database that stores dictionary information on various languages using the first word is searched, so as to provide the user with the corresponding word.

Abstract: A semiconductor apparatus includes a clock path, a command path, a delay monitoring circuit, and an output control circuit. The clock path generates a delay clock signal by delaying a clock signal. The command path generates an output command signal from on one of a command signal and the clock signal, based on a monitoring signal. The delay monitoring circuit generates a delay control signal and a latency control signal based on a phase difference between the delay clock signal and the output command signal, when the monitoring signal is enabled. The output control circuit generates an output enable signal by synchronizing the output command signal with the delay clock signal, based on the latency control signal.

Abstract: The present invention relates to a novel use of NCKAP1 gene in neurodegenerative diseases. More specifically, the present invention relates to a marker composition for predicting the prognosis of a neurodegenerative disease, comprising a NCKAP1 protein or a gene encoding same, a composition and a kit for predicting the prognosis of a neurodegenerative disease, which comprises a formulation for measuring the level of the protein or an mRNA of the gene encoding same, and a pharmaceutical composition for preventing or treating neurodegenerative disease, comprising the protein or the gene encoding same as an active ingredient.

Abstract: A semiconductor device and command generation method, the semiconductor device includes a command recovery circuit configured to receive a command from a plurality of commands, to store a code signal which is generated by encoding the received command from the plurality of commands, depending on the received command, and generate a plurality of internal commands by decoding a command code signal which is generated from the code signal after shifting the received command depending on a shifting control signal; and a memory circuit configured to perform an internal operation depending on the plurality of internal commands.

Abstract: A signal generation circuit generates a first synchronization signal by delaying a first input signal in synchronization with a first division clock signal, and generates a second synchronization signal by delaying a second input signal in synchronization with a second division clock signal. The signal generation circuit adjusts pulse widths of the first and second synchronization signals based on an on-control signal and an off-control signal. The signal generation circuit includes a retiming circuit configured to generate an output signal by retiming a preliminary output signal, generated from the first and second synchronization signals, based on the first and second division clock signals.

Abstract: A strobe signal generation circuit includes a trigger circuit configured to generate a pull-up signal and a pull-down signal according to a clock signal; a first main driver configured to generate a differential data strobe signal in response to receiving the pull-up signal and the pull-down signal; and a second main driver configured to generate an other differential data strobe signal in response to receiving the pull-up signal and the pull-down signal from among the at least one pull-down signal through opposite terminals than the first main driver received the pull-up signal and the pull-down signal.