Abstract: An electronic device including a protection layer, a display panel, and a sound broadcasting element is provided. The protection layer has an inner surface and a side surface directly connected to the inner surface. The display panel is disposed on the inner surface of the protection layer and has a back surface and a side surface directly connected to the back surface. The sound broadcasting element is located adjacent to the side surface of the display panel, and the sound broadcasting element includes a piezoelectric component and a connection component.

Abstract: An electronic device has a narrow viewing angle state and a wide viewing angle state, and includes a panel and a light source providing a light passing through the panel. In the narrow viewing angle state, the light has a first relative light intensity and a second relative light intensity. The first relative light intensity is the strongest light intensity, the second relative light intensity is 50% of the strongest light intensity, the first relative light intensity corresponds to an angle of 0°, the second relative light intensity corresponds to a half-value angle, and the half-value angle is between ?15° and 15°. In the narrow angle state, a third relative light intensity at each angle between 20° and 60° or each angle between ?20° and ?60° is lower than 20% of the strongest light intensity.

Abstract: A method includes receiving a wafer, measuring a surface topography of the wafer; calculating a topographical variation based on the surface topography measurement performing a single-zone alignment compensation when the topographical variation is less than a predetermined value or performing a multi-zone alignment compensation when the topographical variation is greater than the predetermined value; and performing a wafer alignment according to the single-zone alignment compensation or the multi-zone alignment compensation.

Abstract: A packaging method for a tire pressure monitoring sensor includes a step of placing, a step of pouring, and a step of hardening. In the step of placing, a sensing transmission module is put into a cavity of a modeling unit, and a positioning portion in the cavity restricts the sensing transmission module from moving transversely and toward an inner bottom of the cavity. In the step of pouring, a rubber compound is poured into the cavity and fills the cavity. The sensing transmission module is coated by the rubber compound to form a case on the outer surface of the sensing transmission module. In the step of hardening, the case is hardened and integrally formed with the sensing transmission module to form a tire pressure monitoring sensor which is removed from the cavity.

Abstract: A bottom lens for an immersion exposure tool includes a hydrophobic coating on the sidewalls of the bottom lens. A bottom portion of the bottom lens is not coated with the hydrophobic coating to maintain the optical performance of the bottom lens and to not distort a pattern that is to be transferred to a substrate. The hydrophobic coating may reduce the thermal instability of the bottom lens. This may reduce overlay variation during operation of the immersion exposure tool, which may increase manufacturing yield, decrease device failures, and/or decrease rework and repairs.

Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Abstract: A heat exchanger is provided, including a first case, a second case, a substrate, an engaging structure, an evaporator, a condenser, a first tube, and a second tube. The first case includes a first plate structure and a first protruding structure. The first plate structure has a first inner surface. The first protruding structure protrudes from the first inner surface. The second case includes a second plate structure and a second protruding structure. The second plate structure has a second inner surface. The second protruding structure protrudes from the second inner surface. The substrate is engaged with the first inner surface, the first protruding structure, the second inner surface, and the second protruding structure via the engaging structure. The substrate is in contact with at least three different lateral surfaces of the engaging structure so that the substrate and the first case combine are bonded.

Abstract: A semiconductor device includes a gate structure extending along a first lateral direction. The semiconductor device includes a source/drain structure disposed on one side of the gate structure along a second lateral direction, the second lateral direction perpendicular to the first lateral direction. The semiconductor device includes an air gap disposed between the gate structure and the source/drain structure along the second lateral direction, wherein the air gap is disposed over the source/drain structure.

Abstract: A chip package includes a substrate, a semiconductor chip, and a thermal conductive structure. The chip package includes a first and a second support structures below the thermal conductive structure. The first and the second support structures connect the substrate and corners of the thermal conductive structure. The thermal conductive structure has a side edge connecting the first and the second support structures. The first and the second support structures and the side edge together define of an opening exposing a space surrounding the semiconductor chip. The first and the second support structures are disposed along a side of the substrate. The first support structure is laterally separated from the side of the substrate by a first lateral distance. The side edge of the thermal conductive structure is laterally separated from the side of the substrate by a second lateral distance different than the first lateral distance.

Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

Abstract: A semiconductor device is described. An isolation region is disposed on the substrate. A plurality of channels extend through the isolation region from the substrate. The channels including an active channel and an inactive channel. A dummy fin is disposed on the isolation region and between the active channel and the inactive channel. An active gate is disposed over the active channel and the inactive channel, and contacts the isolation region. A dielectric material extends through the active gate and contacts a top of the dummy fin. The inactive channel is a closest inactive channel to the dielectric material. A long axis of the active channel extends in a first direction. A long axis of the active gate extends in a second direction. The active channel extends in a third direction from the substrate. The dielectric material is closer to the inactive channel than to the active channel.

Abstract: A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate supporting and electrically connected to the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment connected to the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.

Abstract: A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has an U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

Abstract: Provided are a system and a method for optimization of network function management and computer readable medium thereof that develop an OAM system architecture compatible with a standard MANO framework set by ETSI, so as to effectively integrate and manage the resources and situation configurations of the network elements (including VNF and CNF) of different manufacturers. Therefore, containment management for various network elements may be flexibly integrated, advantages of the standard MANO framework may be preserved, cost for customized development of various OAM systems and the information transmission therefrom may be reduced, and overall efficiency is increased.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

Abstract: A method is provided, including following operations: activating a first word line to couple a first bit line with a second bit line to form a first conductive loop through a first transistor having a first terminal coupled to the first bit line and a second transistor having a first terminal coupled to the second bit line, wherein second terminals of the first and second transistors are coupled together; activating a second word line to couple a third bit line with a fourth bit line to form a second conductive loop, wherein the first and second word lines are disposed below the first to fourth bit lines; and identifying that the first conductive loop, the second conductive loop, or the combinations thereof is short-circuited or open-circuited.

Abstract: A method includes providing a workpiece to a semiconductor apparatus, the workpiece including a material layer including a first strip having: a first plurality of exposure fields; and a second plurality of exposure fields alternatingly arranged with the first plurality of exposure fields. The method further includes: scanning the first strip along a first scan route from a first side of the workpiece to a second side of the workpiece to generate first topography measurement data; scanning the first strip along a second scan route from the second side to the first side to generate second topography measurement data; and exposing the first plurality of exposure fields and exposing the second plurality of exposure fields according to the first topography measurement data and the second topography measurement data.

Abstract: A shower curtain rod contains: multiple coupling posts and multiple rotatable connection assemblies. A respective one rotatable connection assembly includes: a first connector, a second connector, a flexible seat, and a fixing bolt. The first connector has a first locating portion and a first rotatable joining portion. The first rotatable joining portion has a through hole and multiple notches. The second connector has a second locating portion and a second rotatable joining portion. The second rotatable joining portion has two opposite tabs and an accommodation groove. The flexible seat is received in the accommodation groove and includes a sole plate and two side plates. A respective one side plate has a passing aperture, a positioning protrusion, and at least one elastic sheet. The fixing bolt is configured to rotatably connect the first rotatable joining portion in the trench between the two side plates.

Abstract: A heated extreme ultraviolet (EUV) mirror, method of making same, and a projection optics box (POB) of an EUV lithography scanner employing same, are disclosed. The POB includes EUV mirrors disposed inside a vacuum chamber and arranged respective to project an image of a reflective EUV photolithography mask disposed on a reticle stage onto a wafer disposed on a wafer stage. Each EUV mirror of the plurality of EUV mirrors includes a mirror support and an EUV-reflective multilayer disposed on a front side of the mirror support. The plurality of EUV mirrors includes at least one heated EUV mirror that further includes a resistive heater disposed in the mirror support of the heated EUV mirror. In integrated circuit manufacturing, the exposure of a photoresist layer on a semiconductor wafer to EUV light using the POB includes controlling mirror temperature using a heater embedded in the EUV mirror.