Patents by Inventor Ina Ostermay

Ina Ostermay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8906811
    Abstract: A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: December 9, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thorsten Kammler, Andy Wei, Ina Ostermay
  • Patent number: 8728896
    Abstract: When forming sophisticated transistors requiring an embedded semiconductor alloy, the cavities may be formed with superior uniformity on the basis of, for instance, crystallographically anisotropic etch steps by providing a uniform oxide layer in order to reduce process related fluctuations or queue time variations. The uniform oxide layer may be formed on the basis of an APC control regime.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: May 20, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Andreas Ott, Ina Ostermay
  • Patent number: 8466018
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming extension implant regions in a PMOS region and a NMOS region of a semiconducting substrate for a PMOS device and a NMOS device, respectively and, after forming the extension implant regions, performing a first heating process. The method further includes forming a plurality of cavities in the PMOS region of the substrate, performing at least one epitaxial deposition process to form a plurality of in-situ doped semiconductor layers that are positioned in or above each of said cavities, and forming a masking layer that exposes the NMOS region and covers the PMOS region. The method concludes with the steps of forming source/drain implant regions in the NMOS region of the substrate for the NMOS device and performing a second heating process.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: June 18, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Illgen, Stefan Flachowsky, Ina Ostermay
  • Publication number: 20130069123
    Abstract: Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming first doped stressor regions in a first region of semiconductor material, forming second doped stressor regions in a second region of semiconductor material after forming the first doped stressor regions, and after forming the second doped stressor regions, annealing the semiconductor device structure to activate ions of the first and second doped stressor regions concurrently. The amount of time for the annealing is chosen to inhibit diffusion of the ions of the first and second doped stressor regions.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ralf Illgen, Stefan Flachowsky, Ina Ostermay
  • Publication number: 20130032877
    Abstract: When forming sophisticated semiconductor devices including high-k metal gate electrode structures and N-channel transistors, superior performance may be achieved by incorporating epitaxially grown semiconductor materials, for instance a strain-inducing silicon/carbon alloy in combination with an N-doped silicon material, which may provide an acceptable sheet resistivity.
    Type: Application
    Filed: July 16, 2012
    Publication date: February 7, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Ina OSTERMAY, Ralf ILLGEN, Stefan FLACHOWSKY
  • Publication number: 20130029463
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming extension implant regions in a PMOS region and a NMOS region of a semiconducting substrate for a PMOS device and a NMOS device, respectively and, after forming the extension implant regions, performing a first heating process. The method further includes forming a plurality of cavities in the PMOS region of the substrate, performing at least one epitaxial deposition process to form a plurality of in-situ doped semiconductor layers that are positioned in or above each of said cavities, and forming a masking layer that exposes the NMOS region and covers the PMOS region. The method concludes with the steps of forming source/drain implant regions in the NMOS region of the substrate for the NMOS device and performing a second heating process.
    Type: Application
    Filed: July 26, 2011
    Publication date: January 31, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ralf Illgen, Stefan Flachowsky, Ina Ostermay
  • Publication number: 20120231591
    Abstract: Methods are provided for fabricating CMOS integrated circuits. In accordance with one embodiment the methods include forming a gate electrode structure overlying an N-doped portion of a semiconductor substrate and growing an embedded silicon germanium area in the N-doped portion in alignment with the gate electrode structure. A layer of silicon is selectively grown overlying the embedded silicon germanium area and a nickel silicide contact is made to the layer of silicon.
    Type: Application
    Filed: March 11, 2011
    Publication date: September 13, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stefan FLACHOWSKY, Ralf ILLGEN, Ina OSTERMAY, Jan HOENTSCHEL
  • Publication number: 20120161249
    Abstract: When forming sophisticated gate electrode structures in an early manufacturing stage, the threshold voltage characteristics may be adjusted on the basis of a semiconductor alloy, which may be formed on the basis of low pressure CVD techniques. In order to obtain a desired high band gap offset, for instance with respect to a silicon/germanium alloy, a moderately high germanium concentration may be provided within the semiconductor alloy, wherein, however, at the interface formed with the semiconductor base material, a low germanium concentration may significantly reduce the probability of creating dislocation defects.
    Type: Application
    Filed: December 28, 2011
    Publication date: June 28, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Ina Ostermay, Roman Boschke
  • Publication number: 20120153350
    Abstract: Embodiments of semiconductor devices and methods for fabricating the semiconductor devices are provided. The method includes forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure of a transistor. The gate electrode structure is disposed on a channel region of a first silicon-germanium alloy. A strain-inducing silicon-germanium alloy is formed in the cavity and in contact with the first silicon-germanium alloy. The strain-inducing silicon-germanium alloy includes carbon and has a composition different from the first silicon-germanium alloy.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Stephan KRONHOLZ, Gunda BEERNINK, Ina OSTERMAY
  • Publication number: 20120153402
    Abstract: When forming sophisticated transistors requiring an embedded semiconductor alloy, the cavities may be formed with superior uniformity on the basis of, for instance, crystallographically anisotropic etch steps by providing a uniform oxide layer in order to reduce process related fluctuations or queue time variations. The uniform oxide layer may be formed on the basis of an APC control regime.
    Type: Application
    Filed: September 21, 2011
    Publication date: June 21, 2012
    Applicant: GLOBAL FOUNDRIES Inc.
    Inventors: Stephan Kronholz, Andreas Ott, Ina Ostermay
  • Publication number: 20120032278
    Abstract: A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.
    Type: Application
    Filed: October 13, 2011
    Publication date: February 9, 2012
    Inventors: Thorsten Kammler, Andy Wei, Ina Ostermay
  • Patent number: 8053273
    Abstract: A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: November 8, 2011
    Assignee: Advanced Micro Devices Inc.
    Inventors: Thorsten Kammler, Andy Wei, Ina Ostermay
  • Publication number: 20100025779
    Abstract: A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.
    Type: Application
    Filed: July 17, 2009
    Publication date: February 4, 2010
    Inventors: Thorsten Kammler, Andy Wei, Ina Ostermay