Abstract: A forwarding method and system for data broadcast reduction in a Vehicle Named Data Networking (VNDN) is proposed. The method includes (a) setting name centrality (NameCent) count data with respect to an interest packet received by a node of the VNDN; (b) measuring, by a Received Signal Strength Indicator (RSSI), a power level of signal received from an access point (AP) or any other vehicle in wireless communication; (c) calculating a weight of the interest packet for a data forwarder in a current node or a previous node based on the name centrality (NameCent) count data and signal strength measured by the Received Signal Strength Indicator (RSSI); and (d) determining a potential forwarder of a data packet by comparison of variables of the weight calculated in step (c).

Abstract: A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.

Abstract: A transmission node includes a digital front-end device that provides functional clocks for JESD204B based data transmission. The front-end device includes a PLL for generating a phase locked clock based on a device clock of the front-end device, a clock dividing unit for generating the functional clocks by dividing the phase locked clock, a clock gating unit connected between the PLL and the clock dividing unit, and a system reference signal sampling unit for timing radio frame boundaries. The clock gating unit gates the phase locked clock to align the functional clocks with the device clock within a predetermined number of cycles of the phase locked clock, upon locking of the PLL or receipt of a system resynchronization request. The system reference signal sampling unit samples the system reference signal with zero-cycle latency between device clock and phase locked clock.

Abstract: A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.

Abstract: A system for isolating a first power domain from a second power domain in an integrated circuit includes receiving an input signal from the first power domain and receiving a set of bits from a programmable register. An isolation enable signal indicative of isolating the first power domain from the second power domain is generated, and an intermediate signal based on the isolation enable signal and the input signal is generated. At least one of the input signal, a logic low signal, a logic high signal, and the intermediate signal is output based on the isolation enable signal and the set of bits.

Abstract: An integrated circuit (IC) in an unresponsive radio equipment (RE) node includes a common public radio interface (CPRI) controller, a processor, and a system reset controller that includes an L1 (Layer 1) reset controller. The CPRI controller generates a reset request signal based on a CPRI reset request received from an RE controller (REC). The L1 reset controller generates a traffic stop signal based on the reset request signal. The CPRI controller generates a traffic idle signal based on the traffic stop signal. The L1 reset controller receives the traffic idle signal before a predetermined time period and generates a system reset signal for resetting the processor, thereby recovering the unresponsive RE node without disrupting the network topology of a communication system that includes the REC and multiple RE nodes including the unresponsive RE node connected via a CPRI link.

Abstract: A transmission node includes a digital front-end device that provides functional clocks for JESD204B based data transmission. The front-end device includes a PLL for generating a phase locked clock based on a device clock of the front-end device, a clock dividing unit for generating the functional clocks by dividing the phase locked clock, a clock gating unit connected between the PLL and the clock dividing unit, and a system reference signal sampling unit for timing radio frame boundaries. The clock gating unit gates the phase locked clock to align the functional clocks with the device clock within a predetermined number of cycles of the phase locked clock, upon locking of the PLL or receipt of a system resynchronization request. The system reference signal sampling unit samples the system reference signal with zero-cycle latency between device clock and phase locked clock.

Abstract: A programmable clock divider includes first and second comparators for generating first and second signals respectively based on a count value of a counter and a frequency ratio value. First and second flip-flops delay the first and second signals by one clock cycle of the input clock signal. An active-low latch delays the second signal by half a clock cycle of the input clock signal. A multiplexer receives the delayed first and second signals at first and second input terminals respectively and the input clock signal at a select terminal, and generates a divided clock signal. The multiplexer outputs the second delayed signal when the input clock signal is at a logic high state and outputs the first delayed signal when the input clock signal is at a logic low state.