Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.

Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.

Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.

Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.

Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.

Abstract: Some embodiments include apparatus and methods using a first digital-to-time converter (DTC) circuit to receive an input clock signal and generate a first clock signal based on the input clock signal, a second DTC circuit to receive the input clock signal and generate a second clock signal based on the input clock signal, and an output circuit to receive the first and second clock signals to generate an output clock signal based on the first and second clock signals.

Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.

Abstract: Some embodiments include apparatus and methods using a first digital-to-time converter (DTC) circuit to receive an input clock signal and generate a first clock signal based on the input clock signal, a second DTC circuit to receive the input clock signal and generate a second clock signal based on the input clock signal, and an output circuit to receive the first and second clock signals to generate an output clock signal based on the first and second clock signals.

Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.

Abstract: Some embodiments include apparatus and methods using a first digital-to-time converter (DTC) circuit to receive an input clock signal and generate a first clock signal based on the input clock signal, a second DTC circuit to receive the input clock signal and generate a second clock signal based on the input clock signal, and an output circuit to receive the first and second clock signals to generate an output clock signal based on the first and second clock signals.

Abstract: A system includes a digital-to-time converter (DTC) to generate output signals with phase offsets set by a plurality of DTC input values and a time-to-digital converter (TDC) operatively coupled to the DTC, wherein the TDC has a lower resolution than the DTC. The system also includes a processing component operatively coupled to the DTC and the TDC. The processing device, for each of a plurality of TDC thresholds, determines a DTC input value corresponding to a respective TDC threshold. The processing device may then generate a calibration function based on the determined DTC input values and corresponding TDC thresholds.

Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.