Abstract: Methods for generating constraints associated with an integrated circuit design are provided. The method includes identifying, with a processor, a plurality of paths based on a floor-plan data set, each of the paths specifying a first block, a second block, and a first interconnect between the first block and the second block. Cycle time criteria is determined for each of the plurality of paths. A total delay is estimated for each of the plurality of paths based on a block-to-block delay and an in-block delay, wherein the block-to-block delay is based on the interconnect data associated with the first interconnect, and the in-block delay is based on the cell data associated with the first and second blocks.