Abstract: Resistor structures of stacked devices and methods of forming the same are provided. The, resistor structures may include a substrate, an upper semiconductor layer that may be spaced apart from the substrate in a vertical direction, a lower semiconductor layer that may be between the substrate and the upper semiconductor layer, and first and second resistor contacts that may be spaced apart from each other in a horizontal direction. At least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate may contact the first and second resistor contacts.

Abstract: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a static random access memory (SRAM) unit. The SRAM unit may include a first inverter on a substrate and a power distribution network (PDN) structure including a first power rail and a second power rail. The substrate may extend between the first inverter and the PDN structure. The first inverter may include a first upper transistor including a first upper source/drain region, a first lower transistor between the substrate and the first upper transistor and including a first lower source/drain region, a first power contact extending through the substrate and electrically connecting the first upper source/drain region to the first power rail, and a second power contact extending through the substrate and electrically connecting the first lower source/drain region to the second power rail.

Abstract: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

Abstract: A multi-stack semiconductor device includes: a lower-stack transistor structure including a lower active region and a lower gate structure, the lower active region including a lower channel structure, and the lower gate structure surrounding the lower channel structure; an upper-stack transistor structure vertically stacked above the lower-stack transistor structure, and including an upper active region and an upper gate structure, the upper active region including an upper channel structure, and the upper gate structure surrounding the upper channel structure; and at least one gate contact plug contacting a top surface of the lower gate structure, wherein the lower gate structure and the upper gate structure have a substantially same size in a plan view, and wherein the lower gate structure is not entirely overlapped by the upper gate structure in a vertical direction.

Abstract: A semiconductor device including a wafer, a first semiconductor device and a second semiconductor device on a front side of the wafer, power rails on a back side of the wafer, a backside power distribution network (PDN) grid on the back side of the wafer, and front-side signal routing lines above the first and second semiconductor devices on the front side of the wafer. The second semiconductor device is stacked on the first semiconductor device, the backside PDN grid is coupled to the power rails, and the power rails are coupled to the first and second semiconductor devices.

Abstract: A semiconductor memory device comprising a substrate having first and second surfaces opposite to each other, a lower active region on the first surface and including a first lower gate electrode and a first lower active contact, an upper active region on the lower active region and including a first upper gate electrode and a first upper active contact that vertically overlap at least a part of the first lower active contact, a first connection structure vertically connecting the first upper active contact to the first lower active contact, a first metal layer on the first surface, and a backside metal layer on the second surface. The first upper gate electrode and the first lower gate electrode are connected and form a first gate electrode. The first metal layer includes a first node line electrically connecting the first gate electrode to the first upper active contact.

Abstract: A three-dimensional (3D) semiconductor device includes a substrate including a first surface and a second surface that are opposite to each other, a lower active region on the first surface of the substrate, the lower active region including a lower channel pattern and a lower source/drain pattern that are electrically connected to each other, an upper active region on the lower active region, the upper active region including an upper channel pattern and an upper source/drain pattern that are electrically connected to each other, a dam pattern that vertically extends from the lower source/drain pattern to the upper source/drain pattern, a lower active contact electrically connected to the lower source/drain pattern, an upper active contact electrically connected to the upper source/drain pattern, and a vertical via that vertically extends along the dam pattern to electrically connect the lower active contact to the upper active contact.

Abstract: A semiconductor device includes a substrate; a 1st transistor formed above the substrate, and having a 1st transistor stack including a plurality of 1st channel structures, a 1st gate structure surrounding the 1st channel structures, and 1st and 2nd source/drain regions at both ends of the 1st transistor stack in a 1st channel length direction; and a 2nd transistor formed above the 1st transistor in a vertical direction, and having a 2nd transistor stack including a plurality of 2nd channel structures, a 2nd gate structure surrounding the 2nd channel structures, and 3rd and 4th source/drain regions at both ends of the 2nd transistor stack in a 2nd channel length direction, wherein the 3rd source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region, and the 4th source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region.

Abstract: A stacked integrated circuit device, including a lower active region, a lower gate pattern surrounding the lower active region, a lower dielectric layer between the lower active region and the lower gate pattern, an intermediate insulating layer on the lower active region, an upper active region on the intermediate insulating layer, an upper gate pattern surrounding the upper active region and covering the lower gate pattern, and an upper dielectric layer between the upper active region and the upper gate pattern, wherein an upper surface of the lower gate pattern is located lower in a vertical direction than an upper surface of the intermediate insulating layer, and the lower gate pattern surrounds at least a portion of a side surface of the intermediate insulating layer.

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

Abstract: A 3D stacked FET may include a back-side wiring layer including a first back-side power line and a second back-side power line, a first FET on the back-side wiring layer, a second FET over the first FET, a front-side wiring layer over the second FET, a first through-electrode connecting the first FET to the second FET, and a second through-electrode connecting the front-side and back-side power lines. The front-side wiring layer may extend in a first direction and may include a front-side power line connected to the second back-side power line. The first FET and the second FET may share a gate extending in a second direction. Each of the first FET and the second FET may include a source and a drain respectively on both sides of the gate in the first direction, and a channel between the source and the drain and surrounded by the gate.

Abstract: An integrated circuit device is provided. The device includes: lower source/drain areas; lower contacts respectively on bottom surfaces of the lower source/drain areas; upper source/drain areas spaced apart from the lower source/drain areas in a vertical direction; upper contacts respectively on upper surfaces of the upper source/drain areas; and a first vertical conductive rail electrically connected to a first contact of the lower contacts and the upper contacts, the first vertical conductive rail extending in the vertical direction, and including a first portion having a first upper surface at a first vertical level and a second portion having a second upper surface at a second vertical level lower than the first vertical level. The second portion overlaps a first upper contact among the upper contacts in the vertical direction.

Abstract: A multi-stack semiconductor device includes: a lower-stack transistor structure including a lower active region and a lower gate structure, the lower active region including a lower channel structure, and the lower gate structure surrounding the lower channel structure; an upper-stack transistor structure vertically stacked above the lower-stack transistor structure, and including an upper active region and an upper gate structure, the upper active region including an upper channel structure, and the upper gate structure surrounding the upper channel structure; and at least one gate contact plug contacting a top surface of the lower gate structure, wherein the lower gate structure and the upper gate structure have a substantially same size in a plan view, and wherein the lower gate structure is not entirely overlapped by the upper gate structure in a vertical direction.

Abstract: An integrated circuit device includes a lower insulating line extending in a first direction, a plurality of lower channel lines over the lower insulating line, first and second lower gate lines respectively on opposing sides of the lower insulating line and opposing sides of one of the lower channel lines, a third lower gate line extending around upper and lower surfaces of the one of the lower channel line and connecting the first and second lower gate lines to each other, an outer gate line arranged under the lower insulating line and contacting the first and second lower gate lines, an upper insulating line over an upper surface of each lower channel line, a plurality of upper channel lines over the upper insulating line, and an upper gate line extending around one of the upper channel lines.

Abstract: A semiconductor device includes: an active area that protrudes from an upper surface of a substrate and extends parallel to the upper surface of the substrate; an element isolating area formed on the substrate and around the active area; a channel formed on an upper surface of the active area; a gate structure that surrounds at least two surfaces of the channel; a spacer formed on both sidewalls of the gate structure; and a source/drain layer in contact with both sidewalls of the channel and insulated from the gate structure by the spacer. The gate structure includes, in a cross-section, a first portion whose width in a first direction increases from an upper portion of the gate structure toward a lower portion closer to the substrate, and a second portion whose width in the first direction remains the same or decreases below the first portion.

Abstract: A semiconductor device including a static random access memory (SRAM) in a three-dimensional (3D) stack is provided. The semiconductor device includes a first transistor stack including a first channel and a first gate, a second transistor stack including a second channel and a second gate, the second transistor stack being disposed above the first transistor stack, a bit line disposed on a first portion of an upper surface of the first channel, a voltage source disposed on a first portion of an upper surface of the second channel and a first shared contact connecting the first channel to the second channel, where a width of the second channel is less than a width of the first channel.

Abstract: A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a static random access memory (SRAM) unit. The SRAM unit may include a first inverter on a substrate and a power distribution network (PDN) structure including a first power rail and a second power rail. The substrate may extend between the first inverter and the PDN structure. The first inverter may include a first upper transistor including a first upper source/drain region, a first lower transistor between the substrate and the first upper transistor and including a first lower source/drain region, a first power contact extending through the substrate and electrically connecting the first upper source/drain region to the first power rail, and a second power contact extending through the substrate and electrically connecting the first lower source/drain region to the second power rail.