Abstract: A method, apparatus, and manufacture to facilitate power-efficient register file access for preparing a register file to be accessed. Efficient operation of a processor is facilitated while still conserving power. Register information can be decoded during the first phase of a clock to make a determination as to which register within a register file should be accessed. Furthermore, a determination can be made using logic modules as to whether the register information will actually be required by an execution unit during a second phase of the clock. Upon a determination that the register should be enabled, the register is enabled to allow the contents of the register to be output. In this fashion, power can be conserved when it is determined that the information stored by a register file is not required. Such a determination might be made, for example, when it is learned that the information in the register should be bypassed as invalid or an exception occurs cancelling the instruction.