Patents by Inventor Inder M. Sodhi
Inder M. Sodhi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126353Abstract: A power converter circuit included in a computer system may include a phase circuit and a sample circuit. The phase circuit compares a voltage level of the regulated power supply node to a reference voltage to generate a demand current that is used to adjust the voltage level of the regulated power supply node. The phase circuit also digitizes the demand current and stores the resultant bit stream in a memory circuit. The sample circuit generates timestamp information that points to particular storage locations in the memory circuit that correspond to trigger events, allowing the operation of the power converter circuit to be analyzed during different circumstances as well as to adjust operating parameters of the power converter circuit.Type: ApplicationFiled: October 30, 2023Publication date: April 18, 2024Inventors: Shawn Searles, Fabio Gozzini, Sanjay Pant, Inder M. Sodhi
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Patent number: 11960341Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Different sets of power delivery trigger circuits may be coupled to the integrated circuit by wiring or serial communication interfaces. Power reduction responses may be implemented at faster rates utilizing the wired power delivery trigger circuits while slower power reduction response can be implemented utilizing serially connected power delivery trigger circuits. The threshold for power reduction response by wired power delivery trigger circuits may also be closer to a functional failure point of the integrated circuit in order to provide fast response to avoid failure of the integrated circuit.Type: GrantFiled: February 21, 2022Date of Patent: April 16, 2024Assignee: Apple Inc.Inventors: Jamie L. Langlinais, Inder M. Sodhi, Lior Zimet, Keith Cox
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Patent number: 11953967Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.Type: GrantFiled: April 26, 2023Date of Patent: April 9, 2024Assignee: Apple Inc.Inventors: Shawn Searles, Preethi Damodaran, Ofir Gilad, Michele De Fazio, Inder M. Sodhi, Enrico Zanetti, Olivier Girard, Lothar Münch, Andrea Barsanti, Andrea Lazzeri
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Patent number: 11934240Abstract: Techniques are disclosed relating to thermal control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor thermal conditions, implement control for one or more thermal loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid thermal issues, potentially with reduced impact on processor performance relative to traditional techniques.Type: GrantFiled: May 18, 2022Date of Patent: March 19, 2024Assignee: Apple Inc.Inventors: Inder M. Sodhi, Achmed R. Zahir, Carmel Yamberger, Daniele Perretta, Jan Krellner, Ron Neuman, James S. Ismail, Keith Cox
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Patent number: 11899523Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state.Type: GrantFiled: September 19, 2022Date of Patent: February 13, 2024Assignee: Apple Inc.Inventors: Inder M. Sodhi, Achmed R. Zahir, Lior Zimet, Liran Fishel, Omri Flint, Ami Schwartzman
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Patent number: 11868192Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g., with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.Type: GrantFiled: November 17, 2021Date of Patent: January 9, 2024Assignee: Apple Inc.Inventors: Joseph T. DiBene, II, Inder M. Sodhi, Keith Cox, Gerard R. Williams, III
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Patent number: 11853140Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Specifically, a power manager circuit in an integrated circuit (e.g., a system on a chip) may modify power budgets for various components in the integrated circuit to reduce the amount of power control caused by external signaling that indicates a voltage regulator overload (e.g., a voltage droop).Type: GrantFiled: February 21, 2022Date of Patent: December 26, 2023Assignee: Apple Inc.Inventors: Doron Rajwan, Karl Daniel Wulcan, Tal Kuzi, Inder M. Sodhi, Achmed R. Zahir
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Publication number: 20230384846Abstract: A hierarchical, scalable power delivery system is disclosed. The power delivery system includes a first level of power converter circuitry configured to generate one or more first level regulated supply voltages, and a second level of power converter circuitry configured to generate one or more second level regulated supply voltages. The first level of power converter circuitry receives an input supply voltage, while the second level power converter circuitry receives the one or more first level supp1 voltages. The second level power converter circuitry is configured to provide the second level regulated supply voltages to a computing element configured to operate as a single, logical computer system, the computing element being configured to operate in a number of power configurations having differing numbers of load circuits. Different portions of the hierarchical power delivery system may be selectively enabled for corresponding ones of the power configurations of the computing element.Type: ApplicationFiled: May 31, 2023Publication date: November 30, 2023Inventors: Keith Cox, Jamie L. Langlinais, Inder M. Sodhi
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Publication number: 20230376091Abstract: Techniques are disclosed relating to thermal control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor thermal conditions, implement control for one or more thermal loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid thermal issues, potentially with reduced impact on processor performance relative to traditional techniques.Type: ApplicationFiled: May 18, 2022Publication date: November 23, 2023Inventors: Inder M. Sodhi, Achmed R. Zahir, Carmel Yamberger, Daniele Perretta, Jan Krellner, Ron Neuman, James S. Ismail, Keith Cox
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Patent number: 11822409Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.Type: GrantFiled: November 1, 2022Date of Patent: November 21, 2023Assignee: Daedauls Prime LLCInventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
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Patent number: 11803219Abstract: A power converter circuit included in a computer system may include a phase circuit and a sample circuit. The phase circuit compares a voltage level of the regulated power supply node to a reference voltage to generate a demand current that is used to adjust the voltage level of the regulated power supply node. The phase circuit also digitizes the demand current and stores the resultant bit stream in a memory circuit. The sample circuit generates timestamp information that points to particular storage locations in the memory circuit that correspond to trigger events, allowing the operation of the power converter circuit to be analyzed during different circumstances as well as to adjust operating parameters of the power converter circuit.Type: GrantFiled: March 24, 2021Date of Patent: October 31, 2023Assignee: Apple Inc.Inventors: Shawn Searles, Fabio Gozzini, Sanjay Pant, Inder M. Sodhi
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Publication number: 20230333625Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.Type: ApplicationFiled: April 26, 2023Publication date: October 19, 2023Inventors: Shawn Searles, Preethi Damodaran, Ofir Gilad, Michele De Fazio, Inder M. Sodhi, Enrico Zanetti, Olivier Girard, Lothar Münch, Andrea Barsanti, Andrea Lazzeri
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Patent number: 11698669Abstract: A hierarchical, scalable power delivery system is disclosed. The power delivery system includes a first level of power converter circuitry configured to generate one or more first level regulated supply voltages, and a second level of power converter circuitry configured to generate one or more second level regulated supply voltages. The first level of power converter circuitry receives an input supply voltage, while the second level power converter circuitry receives the one or more first level supply voltages. The second level power converter circuitry is configured to provide the second level regulated supply voltages to a computing element configured to operate as a single, logical computer system, the computing element being configured to operate in a number of power configurations having differing numbers of load circuits. Different portions of the hierarchical power delivery system may be selectively enabled for corresponding ones of the power configurations of the computing element.Type: GrantFiled: August 25, 2021Date of Patent: July 11, 2023Assignee: Apple Inc.Inventors: Keith Cox, Jamie L. Langlinais, Inder M. Sodhi
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Patent number: 11687135Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: September 20, 2021Date of Patent: June 27, 2023Assignee: Tahoe Research, Ltd.Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 11669145Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.Type: GrantFiled: September 15, 2021Date of Patent: June 6, 2023Assignee: Apple Inc.Inventors: Shawn Searles, Preethi Damodaran, Ofir Gilad, Michele De Fazio, Inder M. Sodhi, Enrico Zanetti, Olivier Girard, Lothar Münch, Andrea Barsanti, Andrea Lazzeri
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Publication number: 20230109984Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.Type: ApplicationFiled: January 11, 2022Publication date: April 13, 2023Inventors: Doron Rajwan, Inder M. Sodhi, Keith Cox, Jung Wook Cho, Kevin I. Park, Tal Kuzi
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Publication number: 20230101217Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.Type: ApplicationFiled: January 11, 2022Publication date: March 30, 2023Inventors: Doron Rajwan, Inder M. Sodhi, Keith Cox, Jung Wook Cho, Kevin I. Park, Tal Kuzi
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Publication number: 20230080624Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.Type: ApplicationFiled: September 15, 2021Publication date: March 16, 2023Inventors: Shawn Searles, Preethi Damodaran, Ofir Gilad, Michele De Fazio, Inder M. Sodhi, Enrico Zanetti, Olivier Girard, Lothar Münch, Andrea Barsanti, Andrea Lazzeri
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Publication number: 20230069344Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Different sets of power delivery trigger circuits may be coupled to the integrated circuit by wiring or serial communication interfaces. Power reduction responses may be implemented at faster rates utilizing the wired power delivery trigger circuits while slower power reduction response can be implemented utilizing serially connected power delivery trigger circuits. The threshold for power reduction response by wired power delivery trigger circuits may also be closer to a functional failure point of the integrated circuit in order to provide fast response to avoid failure of the integrated circuit.Type: ApplicationFiled: February 21, 2022Publication date: March 2, 2023Inventors: Jamie L. Langlinais, Inder M. Sodhi, Lior Zimet, Keith Cox
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Publication number: 20230069510Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.Type: ApplicationFiled: November 1, 2022Publication date: March 2, 2023Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi