Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

Abstract: Embodiments of the invention relate to energy efficient and conserving thermal throttling of electronic device processors using a zero voltage processor state. For example, a processor die may include a power control unit (PCU), and an execution unit having power gates and a thermal sensor. The PCU is attached to the thermal sensor to determine if a temperature of the execution unit has increased to greater than an upper threshold, such as while the execution unit is processing data in an active processor power state. The PCU is also attached to the power gates so that upon such detection, it can change the active processor power state to a zero processor power state to reduce the temperature of the execution unit. When the sensor detects that the temperature has decreased to less than a lower threshold, the PCU can change the processor power state back to the active state.

Abstract: Embodiments of the invention relate to improving exit latency from computing device processor core deep power down. Processor state data may be maintained during deep power down mode by providing a secondary uninterrupted voltage supply to always on keeper circuits that reside within critical state registers of the processor. When these registers receive a control signal indicating that the processor power state is going to be reduced from an active processor power state to a zero processor power state, they write critical state data from the critical state register latches to the keeper circuits that are supplied with the uninterrupted power. Then, when a register receives a control signal indicating that a processor power state of the processor is going to be increased back to an active processor power state, the critical state data stored in the keeper circuits is written back to the critical state register latches.

Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enhanced temperature based voltage control are described. In one embodiment, an apparatus includes a processor and a controller coupled with the processor. In one embodiment, the controller receives a temperature measurement corresponding to a current temperature of the processor. In one embodiment, the controller further determines an adjustment to a voltage being applied to the processor based at least in part on the temperature measurement and a plurality of internal limits of the processor, wherein the determined adjustment to the voltage is based on an inverse temperature dependence relationship between at least one of an operating frequency and a voltage of the processor, and temperature. In one embodiment, the controller provides the determined adjustment to the voltage to a voltage regulator interface.

Abstract: Embodiments of the invention relate to increased energy efficiency and conservation by reducing and increasing an amount of cache available for use by a processor, and an amount of power supplied to the cache and to the processor, based on the amount of cache actually being used by the processor to process data. For example, a power control unit (PCU) may monitor a last level cache (LLC) to identify if the size or amount of the cache being used by a processor to process data and to determine heuristics based on that amount. Based on the monitored amount of cache being used and the heuristics, the PCU causes a corresponding decrease or increase in an amount of the cache available for use by the processor, and a corresponding decrease or increase in an amount of power supplied to the cache and to the processor.

Abstract: An electronic device comprises a central processing unit, a graphics processing un and a power control unit comprising logic to develop a predictive model of power states for a central processing unit in the electronic device, and use the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the central processing unit. Other embodiments may be described.

Abstract: A method and apparatus automatically transferring to an enhanced low-power state of a processor is disclosed. In one embodiment, either all or a portion of a processor core clock distribution grid may be powered down in these enhanced low-power states. In one embodiment, the processor may operate in a reduced power supply voltage and operate at a reduced frequency during these enhanced low-power states. In one embodiment, a portion of the clock distribution grid may be left on to support snoop operations at a reduced frequency.

Abstract: A method and apparatus automatically transferring to an enhanced low-power state of a processor is disclosed. In one embodiment, either all or a portion of a processor core clock distribution grid may be powered down in these enhanced low-power states. In one embodiment, the processor may operate in a reduced power supply voltage and operate at a reduced frequency during these enhanced low-power states. In one embodiment, a portion of the clock distribution grid may be left on to support snoop operations at a reduced frequency.