Abstract: An interrupt mechanism is disclosed. In one embodiment an integrated circuit (IC) is coupled to a number of peripheral devices, via a bus, and includes an interface controller. The interface controller includes a bus engine circuit coupled to receive data from the various ones of the peripheral devices, wherein the data may include various requests. The bus engine circuit also includes decoding circuitry configured to decode the data to determine the nature of the requests. Responsive to determining that interrupt information is stored in one or more of the requests, the interrupt information may be written to one of a number of interrupt registers. An interrupt controller may read the interrupt registers to determine the presence of interrupts, and thus initiate the process to see that they are serviced.

Abstract: An interrupt mechanism is disclosed. In one embodiment an integrated circuit (IC) is coupled to a number of peripheral devices, via a bus, and includes an interface controller. The interface controller includes a bus engine circuit coupled to receive data from the various ones of the peripheral devices, wherein the data may include various requests. The bus engine circuit also includes decoding circuitry configured to decode the data to determine the nature of the requests. Responsive to determining that interrupt information is stored in one or more of the requests, the interrupt information may be written to one of a number of interrupt registers. An interrupt controller may read the interrupt registers to determine the presence of interrupts, and thus initiate the process to see that they are serviced.

Abstract: A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.

Abstract: Some implementations provide techniques and arrangements to migrate threads from a first core of a processor to a second core of the processor. For example, some implementations may identify one or more threads scheduled for execution at a processor. The processor may include a plurality of cores, including a first core having a first characteristic and a second core have a second characteristic that is different than the first characteristic. Execution of the one or more threads by the first core may be initiated. A determination may be made whether to apply a migration policy. In response to determining to apply the migration policy, migration of the one or more threads from the first core to the second core may be initiated.

Abstract: According to one embodiment of the invention, an integrated circuit device at least one compute engine and a control unit. Coupled to the compute engine(s), the control unit is adapted to dynamically control an energy-efficient operating setting of at least one power management parameter for the integrated circuit device after execution of Basic Input/Output System (BIOS) has already completed.

Abstract: In an embodiment, a processor includes a core to execute instructions, an agent to perform an operation independently of the core, a fabric to couple the core and agent and including a plurality of domains and a logic to receive isochronous parameter information from the agent and environmental information of a platform and to generate first and second values, and a power controller to control a frequency of the domains based at least in part on the first and second values. Other embodiments are described and claimed.

Abstract: According to one embodiment of the invention, an integrated circuit device at least one compute engine and a control unit. Coupled to the compute engine(s), the control unit is adapted to dynamically control an energy-efficient operating setting of at least one power management parameter for the integrated circuit device after execution of Basic Input/Output System (BIOS) has already completed.

Abstract: A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.

Abstract: A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.

Abstract: In an embodiment, a processor includes a core to execute instructions, an agent to perform an operation independently of the core, a fabric to couple the core and agent and including a plurality of domains and a logic to receive isochronous parameter information from the agent and environmental information of a platform and to generate first and second values, and a power controller to control a frequency of the domains based at least in part on the first and second values. Other embodiments are described and claimed.

Abstract: Some implementations provide techniques and arrangements to migrate threads from a first core of a processor to a second core of the processor. For example, some implementations may identify one or more threads scheduled for execution at a processor. The processor may include a plurality of cores, including a first core having a first characteristic and a second core have a second characteristic that is different than the first characteristic. Execution of the one or more threads by the first core may be initiated. A determination may be made whether to apply a migration policy. In response to determining to apply the migration policy, migration of the one or more threads from the first core to the second core may be initiated.

Abstract: According to one embodiment of the invention, an integrated circuit device at least one compute engine and a control unit. Coupled to the compute engine(s), the control unit is adapted to dynamically control an energy-efficient operating setting of at least one power management parameter for the integrated circuit device after execution of Basic Input/Output System (BIOS) has already completed.

Abstract: According to one embodiment of the invention, an integrated circuit device at least one compute engine and a control unit.

Abstract: A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.

Abstract: According to one embodiment of the invention, an integrated circuit device comprises an interconnect, at least one compute engine and a control unit. Coupled to the at least one compute engine via the interconnect, the control unit to analyze heuristic information from the at least one compute engine and to increase or decrease a bandwidth of the interconnect based on the heuristic information.

Abstract: Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.

Abstract: Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.

Abstract: Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.

Abstract: A device and method for continually monitoring multiple thermal sensors located at hotspots across a processor. The sensors are connected to a sensor cycling and selection block located at a periphery of the die. The output from the sensor selection block is converted into a digital temperature code. Based on the digital temperature code, thermal events trigger various thermal controls. The thermal event triggers may be software-programmable, providing flexible temperature management.

Abstract: A device and method for continually monitoring multiple thermal sensors located at hotspots across a processor. The sensors are connected to a sensor cycling and selection block located at a periphery of the die. The output from the sensor selection block is converted into a digital temperature code. Based on the digital temperature code, thermal events trigger various thermal controls. The thermal event triggers may be software-programmable, providing flexible temperature management.