Abstract: A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.

Abstract: A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.

Abstract: An extreme ultraviolet lithography pattern stack, including, an inorganic hardmask layer, an under layer on the inorganic hardmask layer, and a resist layer on the under layer, where the inorganic hardmask layer, under layer, and resist layer have a combined thickness in the range of about 8.5 nm to about 70 nm.

Abstract: Embodiments of the present invention provide systems and methods for trapping amines. This in turn mitigates the undesired scumming and footing effects in a photoresist. The polymer brush is grafted onto a silicon nitride surface. The functional groups and molecular weight of the polymer brush provide protons and impose steric hindrance, respectively, to trap amines diffusing from a silicon nitride surface.

Abstract: A method for forming a semiconductor device includes blocking a first region of a wafer and forming a plurality of fins in a second region of the wafer. A protective conformal mask layer is deposited over the plurality of fins in the second region, the second region is blocked, and a plurality of fins are formed in the first region of the wafer using a variety of wet and/or dry etching procedures. The protective conformal mask layer protects the plurality of fins in the second region from the variety of wet and/or dry etching procedures that are used to form the plurality of fins in the first region.

Abstract: An extreme ultraviolet lithography pattern stack, including, an inorganic hardmask layer, an under layer on the inorganic hardmask layer, and a resist layer on the under layer, where the inorganic hardmask layer, under layer, and resist layer have a combined thickness in the range of about 8.5 nm to about 70 nm.

Abstract: A method for semiconductor processing includes removing, from a first region of a semiconductor device, a top layer of a trilayer photoresist structure formed in the first region and a second region of the semiconductor device to expose a middle layer of the trilayer photoresist structure in the first region. The middle layer is disposed between the top layer and a bottom layer of the trilayer photoresist structure. The middle layer and the bottom layer in the first region are removed to expose at least one first structure, the top layer in the second region being removed during the removal of the bottom layer in the first region. The first region is filled to protect the at least one first structure. The middle layer in the second region is removed while the at least one first structure remains protected.

Abstract: An extreme ultraviolet lithography pattern stack, including, an inorganic hardmask layer, an under layer on the inorganic hardmask layer, and a resist layer on the under layer, where the inorganic hardmask layer, under layer, and resist layer have a combined thickness in the range of about 8.5 nm to about 70 nm.

Abstract: A method for semiconductor processing includes forming a trilayer resist structure having a middle layer disposed between a top layer and a bottom layer. The top layer is removed from a first region to expose the middle layer in the first region, and the middle layer and the bottom layer are removed in the first region to expose a structure to be processed. The top layer in a second region is also removed with the bottom layer in the first region. The first region is filled to protect the structure in the first region. The middle layer is removed in the second region while the first region remains protected. The structures in the first region and structures in the second region are exposed.

Abstract: A method for semiconductor processing includes forming a trilayer resist structure having a middle layer disposed between a top layer and a bottom layer. The top layer is removed from a first region to expose the middle layer in the first region, and the middle layer and the bottom layer are removed in the first region to expose a structure to be processed. The top layer in a second region is also removed with the bottom layer in the first region. The first region is filled to protect the structure in the first region. The middle layer is removed in the second region while the first region remains protected. The structures in the first region and structures in the second region are exposed.

Abstract: An extreme ultraviolet lithography pattern stack, including, an inorganic hardmask layer, an under layer on the inorganic hardmask layer, and a resist layer on the under layer, where the inorganic hardmask layer, under layer, and resist layer have a combined thickness in the range of about 8.5 nm to about 70 nm.

Abstract: A method for forming a semiconductor device includes blocking a first region of a wafer and forming a plurality of fins in a second region of the wafer. A protective conformal mask layer is deposited over the plurality of fins in the second region, the second region is blocked, and a plurality of fins are formed in the first region of the wafer using a variety of wet and/or dry etching procedures. The protective conformal mask layer protects the plurality of fins in the second region from the variety of wet and/or dry etching procedures that are used to form the plurality of fins in the first region.

Abstract: An organic planarization layer (OPL) is formed above a functional layer located on a substrate. A titanium-oxide layer is formed above the OPL, wherein forming the titanium-oxide layer comprises titanium, oxide, carbon, and nitrogen. A photoresist layer is patterned above a first portion of the titanium-oxide layer. A second portion of the titanium-oxide layer is removed using a wet stripping technique. The photoresist layer and the OPL are removed using a dry etch technique, wherein the first portion of the titanium-oxide layer remains over a remaining portion of the OPL. The first portion of the titanium-oxide layer and the functional layer are removed using the wet stripping technique. The remaining portion of the OPL is removed using a dry stripping technique.

Abstract: A method for forming a semiconductor device includes blocking a first region of a wafer and forming a plurality of fins in a second region of the wafer. A protective conformal mask layer is deposited over the plurality of fins in the second region, the second region is blocked, and a plurality of fins are formed in the first region of the wafer using a variety of wet and/or dry etching procedures. The protective conformal mask layer protects the plurality of fins in the second region from the variety of wet and/or dry etching procedures that are used to form the plurality of fins in the first region.