Patents by Inventor Indradeep Ghosh

Indradeep Ghosh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6877141
    Abstract: Evaluating a validation vector includes receiving a network having nodes and a target set that includes one or more nodes of the network. The following steps are repeated until the nodes of the target set have been selected. A node is selected from the target set, and a tag is assigned to the node, where the tag represents an error of a value of a variable corresponding to the node. A test environment specifying a propagation path from an input, through the node, and to an output is generated. The test environment is translated into a validation vector, and the tag is propagated to the output according to the validation vector. After repeating the steps, coverage for the validation vectors is determined in accordance with the propagation to evaluate the one or more validation vectors.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: April 5, 2005
    Assignee: Fujitsu Limited
    Inventors: Indradeep Ghosh, Koichiro Takayama, Liang Zhang
  • Patent number: 6823486
    Abstract: Test patterns are generated by generating assignment decision diagrams that represent a register transfer level digital circuit. A nine-valued symbolic algebra is used in which objectives are determined for portions identified in the assignment decision diagram. The objectives are justified and propagated by traversing the assignment decision diagram in which a test environment is found. Heuristics are used if a test environment is not initially found. Using the test environment found, predetermined test vectors are propagated to obtain a system-level test set. Each test set for each portion are concatenated to obtain a complete test set for the register transfer level digital circuit.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: November 23, 2004
    Assignee: Fujitsu Limited
    Inventor: Indradeep Ghosh
  • Publication number: 20040199881
    Abstract: A method for event-driven observability enhanced coverage analysis of a program parses a program into variables and data dependencies, wherein the data dependencies comprise assignments and operations. The method builds a data structure having multiple records, with each record having at least one data dependency, a parent node, and a child node. Each node is linked to a variable. The method computes the value of each variable using the data structure. The method performs tag propagation based, at least in part, on the data dependencies and computed values.
    Type: Application
    Filed: April 1, 2003
    Publication date: October 7, 2004
    Inventors: Indradeep Ghosh, Koichiro Takayama, Liang Zhang
  • Publication number: 20040199836
    Abstract: Propagating an error through a network includes receiving a network having propagation paths and nodes, where a propagation path has one or more nodes and a node is associated with a variable operable to have a value during simulation. A tag of a tag set is assigned to the value. The tag set includes at least two signed tags, positive tag representing a positive error and a negative tag representing a negative error, and an unsigned tag representing an error having an unknown sign. The tag is propagated along the propagation path to yield intermediate tags, where at least one intermediate tag is an unsigned tag formed from at least two signed tags. A final tag is determined in accordance with the intermediate tags in order to propagate an error through the network.
    Type: Application
    Filed: April 1, 2003
    Publication date: October 7, 2004
    Inventors: Indradeep Ghosh, Koichiro Takayama, Liang Zhang
  • Publication number: 20040199807
    Abstract: Generating a test environment includes accessing initial test environments for a network of nodes, where a test environment specifies a propagation or justification path for a node. The following are repeated until satisfactory coverage is achieved or until a predetermined number of iterations is reached. A coverage for each test environment is calculated, and at least two of the test environments are mated to generate next test environments, where the coverage of the at least two test environments is greater than the coverage of the other test environments.
    Type: Application
    Filed: April 1, 2003
    Publication date: October 7, 2004
    Inventors: Indradeep Ghosh, Liang Zhang
  • Publication number: 20040073892
    Abstract: A method for event-driven observability enhanced coverage analysis of a program parses a program into variables and data dependencies, wherein the data dependencies comprise assignments and operations. The method builds a data structure having multiple records, with each record having at least one data dependency, a parent node, and a child node. Each node is linked to a variable. The method computes the value of each variable using the data structure. The method performs tag propagation based, at least in part, on the data dependencies and computed values.
    Type: Application
    Filed: October 14, 2002
    Publication date: April 15, 2004
    Applicant: Fujitsu Limited
    Inventors: Farzan Fallah, Indradeep Ghosh
  • Publication number: 20030149610
    Abstract: A method for strategic planning by an entity includes assessing a current status of the entity to use as a basis to establish a development direction for the entity, seeking opportunities for the entity in a market and establishing a vision for the entity. The method also includes performing an analysis of the market consistent with the vision to determine a set of profitable market segments from the opportunities. The method also includes establishing a marketing plan consistent with the vision to change the current status of the entity and prioritizing a product portfolio based on the marketing plan. The method implements a course of action consistent with the vision and the marketing plan to move the entity from the current status to the development direction.
    Type: Application
    Filed: February 6, 2002
    Publication date: August 7, 2003
    Inventors: Christopher G. Rowan, Sharnaz Motakef, Indradeep Ghosh
  • Patent number: 6463560
    Abstract: A method for testing a controller-data path RTL circuit using a BIST scheme without imposing any major design restrictions on the circuit. A state table is extracted from the controller netlist of the circuit using a state machine extraction program. The untested RTL elements/modules in the circuit are then selected, and the test control and data flow (TCDF) of the circuit are extracted from the controller/data path. Once the TCDF is extracted for the selected RTL elements, a symbolic testability analysis (STA) is performed to obtain test environments for as many untested data path elements as possible. The controller input sequence at the select signals of these test multiplexers needed for the particular test environment is noted and/or stored. A BIST controller is synthesized from the stored input sequences and the circuit is integrated with the BIST components using the thereby determined BIST architecture.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: October 8, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Sudipta Bhawmik, Indradeep Ghosh, Niraj Jha
  • Publication number: 20020032889
    Abstract: Test patterns are generated by generating assignment decision diagrams that represent a register transfer level digital circuit. A nine-valued symbolic algebra is used in which objectives are determined for portions identified in the assignment decision diagram. The objectives are justified and propagated by traversing the assignment decision diagram in which a test environment is found. Heuristics are used if a test environment is not initially found. Using the test environment found, predetermined test vectors are propagated to obtain a system-level test set. Each test set for each portion are concatenated to obtain a complete test set for the register transfer level digital circuit.
    Type: Application
    Filed: May 8, 2001
    Publication date: March 14, 2002
    Inventor: Indradeep Ghosh