Patents by Inventor Indrajit Banerjee

Indrajit Banerjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12038884
    Abstract: An overlay network is augmented to provide more efficient data storage by processing a dataset of high dimension into an equivalent dataset of lower dimension, wherein the data reduction reduces the amount of actual physical data but not necessarily its informational value. Data to be processed (dimensionally-reduced) is received by an ingestion layer and supplied to a learning-based storage reduction application that implements the data reduction technique. The application applies a data reduction algorithm and stores the resulting dimensionally-reduced data sets in the native data storage or third party cloud. To recover the original higher-dimensional data, an associated reverse algorithm is implemented. In general, the application coverts an N dimensional data set to a K dimensional data set, where K<<N. The N dimensional dataset has a high dimension, and the K dimensional dataset has a low dimension.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: July 16, 2024
    Assignee: Akamai Technologies, Inc.
    Inventor: Indrajit Banerjee
  • Publication number: 20230342336
    Abstract: An overlay network is augmented to provide more efficient data storage by processing a dataset of high dimension into an equivalent dataset of lower dimension, wherein the data reduction reduces the amount of actual physical data but not necessarily its informational value. Data to be processed (dimensionally-reduced) is received by an ingestion layer and supplied to a learning-based storage reduction application that implements the data reduction technique. The application applies a data reduction algorithm and stores the resulting dimensionally-reduced data sets in the native data storage or third party cloud. To recover the original higher-dimensional data, an associated reverse algorithm is implemented. In general, the application coverts an N dimensional data set to a K dimensional data set, where K<<N. The N dimensional dataset has a high dimension, and the K dimensional dataset has a low dimension.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 26, 2023
    Applicant: Akamai Technologies, Inc.
    Inventor: Indrajit Banerjee
  • Patent number: 11687497
    Abstract: An overlay network is augmented to provide more efficient data storage by processing a dataset of high dimension into an equivalent dataset of lower dimension, wherein the data reduction reduces the amount of actual physical data but not necessarily its informational value. Data to be processed (dimensionally-reduced) is received by an ingestion layer and supplied to a learning-based storage reduction application that implements the data reduction technique. The application applies a data reduction algorithm and stores the resulting dimensionally-reduced data sets in the native data storage or third party cloud. To recover the original higher-dimensional data, an associated reverse algorithm is implemented. In general, the application coverts an N dimensional data set to a K dimensional data set, where K<<N. The N dimensional dataset has a high dimension, and the K dimensional dataset has a low dimension.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: June 27, 2023
    Assignee: Akamai Technologies Inc.
    Inventor: Indrajit Banerjee
  • Publication number: 20220027328
    Abstract: An overlay network is augmented to provide more efficient data storage by processing a dataset of high dimension into an equivalent dataset of lower dimension, wherein the data reduction reduces the amount of actual physical data but not necessarily its informational value. Data to be processed (dimensionally-reduced) is received by an ingestion layer and supplied to a learning-based storage reduction application that implements the data reduction technique. The application applies a data reduction algorithm and stores the resulting dimensionally-reduced data sets in the native data storage or third party cloud. To recover the original higher-dimensional data, an associated reverse algorithm is implemented. In general, the application coverts an N dimensional data set to a K dimensional data set, where K<<N. The N dimensional dataset has a high dimension, and the K dimensional dataset has a low dimension.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 27, 2022
    Applicant: Akamai Technologies, Inc.
    Inventor: Indrajit Banerjee
  • Publication number: 20100213643
    Abstract: A simple and direct methodology for synthesis of polycrystalline silicon sheets is demonstrated in our invention, where silica (SiO2) and elemental carbon (C) are reacted under RF or MW excitation. These polycrystalline silicon sheets can be directly used as feedstock/substrates for low cost photovoltaic solar cell fabrication. Other techniques, such as textured polycrystalline silicon substrate formation, in situ doping, and in situ formation of p-n junctions, are described, which make use of processing equipments and scheme setups of various embodiments of the invention.
    Type: Application
    Filed: February 25, 2010
    Publication date: August 26, 2010
    Inventors: Prasad N. Gadgil, Rajat Roychoudhury, Mushtaq Mulla, Indrajit Banerjee
  • Publication number: 20040058551
    Abstract: After etching a pattern into a layer of material with a fluorous etch solution, the resulting fluorous post-etch residue is treated with a chemical solution to render the post-etch residue more responsive to polar cleaning solutions. The fluorous post-etch residue, which is normally resistant to removal by polar cleaning solutions, may change its physical and chemical characteristics after being exposed to the chemical solution for a predetermined time and temperature. The residue may then be more easily dissolved and removed with the polar cleaning solution.
    Type: Application
    Filed: September 23, 2002
    Publication date: March 25, 2004
    Inventors: Robert P. Meagley, Vani K. Thirumala, Indrajit Banerjee
  • Patent number: 6566757
    Abstract: An interconnect structure for microelectronic devices includes interconnect lines having dielectric material disposed therebetween as an intralayer dielectric, and a capping structure, also disposed between the interconnect lines, that reduces outgassing from the material. Typical embodiments include fluorinated dielectric materials, such as amorphous fluorinated carbon. The capping structure also acts as a moisture barrier to prevent moisture from penetrating into the fluorinated material and combining therewith to produce corrosive chemicals. The capping structure is formed in-situ so that the fluorinated dielectric material is not exposed to moisture prior to the formation of the capping structure.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: May 20, 2003
    Assignee: Intel Corporation
    Inventors: Indrajit Banerjee, Lawrence D. Wong, Marnie L. Harker
  • Patent number: 6528865
    Abstract: An amorphous fluorocarbon material useful as a thin film low-k dielectric layer is disclosed. This film is deposited in a high density plasma reactor, preferably an electron cyclotron resonance reactor, using helium as the plasma gas. Substituting helium for argon as the plasma gas results in the thin film layer having a number of desirable qualities, including a high hardness, a high modulus, and high thermal stability. These qualities make the film especially useful as an interlayer dielectric material in integrated circuit manufacturing.
    Type: Grant
    Filed: January 22, 1999
    Date of Patent: March 4, 2003
    Assignee: Intel Corporation
    Inventor: Indrajit Banerjee
  • Patent number: 5946601
    Abstract: The present invention is a liner and/or barrier layer that will encapsulate the low k materials and act as a diffusion barrier between the low k material and the surrounding metal layers. As the temperatures of the processing sequence increase the liner and/or barrier layer will decrease the diffusion of fluorine from the low k material into the surrounding metal layers. Thus, the present invention will reduce potential corrosion problems of the metal layers.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: August 31, 1999
    Assignee: Intel Corporation
    Inventors: Lawrence D. Wong, Indrajit Banerjee, Steven Towie
  • Patent number: 4564564
    Abstract: A superconducting tape or wire with an improved critical field is formed of alternating layers of a niobium-containing superconductor such as Nb, NbTi, Nb.sub.3 Sn or Nb.sub.3 Ge with a thickness in the range of about 0.5-1.5 times its coherence length, supported and separated by layers of copper with each copper layer having a thickness in the range of about 170-600 .ANG..
    Type: Grant
    Filed: August 16, 1983
    Date of Patent: January 14, 1986
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: Ivan K. Schuller, John B. Ketterson, Indrajit Banerjee