Patents by Inventor Indrani Paul

Indrani Paul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250112639
    Abstract: An apparatus can include: a processor; a voltage regulator configured to provide a processor voltage and a processor current to the processor; and a voltage regulator controller that can include a current sensor comprising an analog-to-digital converter (ADC) having an ADC input range and configured to provide current data based on an ADC input voltage, and a configuration manager configured to receive processor power data and adjust the ADC input range based on the processor power data. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Wei Han, Meeta Surendramohan Srivastav, LiLi Chen, Indrani Paul
  • Publication number: 20250110538
    Abstract: The disclosed device includes a processing component having various compute blocks, and a control circuit that switches at least one of the compute blocks from a normal voltage rail for the processing component to a second voltage rail in response to power gating a normal voltage rail. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Meeta Surendramohan Srivastav, Indrani Paul, Akila Subramaniam
  • Publication number: 20250110798
    Abstract: Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on the IC, and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.
    Type: Application
    Filed: August 1, 2024
    Publication date: April 3, 2025
    Inventors: INDRANI PAUL, LEONARDO DE PAULA ROSA PIGA, MAHESH SUBRAMONY, SONU ARORA, DONALD CHEREPACHA, ADAM N C CLARK
  • Publication number: 20250112470
    Abstract: The disclosed device includes power circuits that can communicate with a control circuit. In response to a power circuit communicating a low efficiency state, the control circuit can redistribute at least a portion of a load of the power circuit to one or more other power circuits. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: David King Wai Li, Indrani Paul
  • Patent number: 12235708
    Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises a quality of service (QOS) component having first assigned registers used to store data to execute a program, a plurality of non-QOS components having second assigned registers used to store data to execute the program and a power management controller, in communication with the QOS component and the non-QOS components. The power management controller is configured to issue fences for the non-QOS components when it is determined that one or more of the non-QOS components are idle, issue a fence for the QOS component when the fences for the non-QOS components are completed and enter a reduced power state when the fences for the non-QOS components and the fence for the QOS component are completed.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: February 25, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin Tsien, Alexander J. Branover, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry, Mihir Shaileshbhai Doctor
  • Publication number: 20250037750
    Abstract: The disclosed systems and methods include a control circuit for entering a low power state of a memory by preserving a context of the memory's controller and power gating the memory's physical layer. The context can be saved to a non-volatile memory device or by keeping a retention supply voltage to a register of the memory controller. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: July 25, 2024
    Publication date: January 30, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Indrani Paul, Benjamin Tsien, James R. Magro
  • Patent number: 12181944
    Abstract: A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: December 31, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Thomas J. Gibney, Stephen V. Kosonocky, Mihir Shaileshbhai Doctor, John P. Petry, Indrani Paul, Benjamin Tsien, Christopher T. Weaver
  • Publication number: 20240403065
    Abstract: The disclosed device includes multiple special purpose processors that are configured to perform, in parallel, a power on transition sequence for the device, which can involve restoring a data state of components of the device using data stored in local storages of the special purpose processors. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: May 31, 2024
    Publication date: December 5, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Sriram Sambamurthy, Indrani Paul, Kevin M. Brandl, James R. Magro, Zhao Hui Yu, Oswin E. Housty
  • Patent number: 12130692
    Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: October 29, 2024
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Karthik Rao, Indrani Paul, Donny Yi, Oleksandr Khodorkovsky, Leonardo De Paula Rosa Piga, Wonje Choi, Dana G. Lewis, Sriram Sambamurthy
  • Patent number: 12130690
    Abstract: A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: October 29, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Alexander J. Branover, Christopher T. Weaver, Benjamin Tsien, Indrani Paul, Mihir Shaileshbhai Doctor, Thomas J. Gibney, John P. Petry, Dennis Au, Oswin Hall
  • Patent number: 12111716
    Abstract: A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: October 8, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mihir Shaileshbhai Doctor, Alexander J. Branover, Benjamin Tsien, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry
  • Patent number: 12086009
    Abstract: Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: September 10, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Thomas J. Gibney, Mihir Shaileshbhai Doctor, Indrani Paul, Benjamin Tsien, Stephen V. Kosonocky, John P. Petry, Christopher T. Weaver
  • Patent number: 12072754
    Abstract: A method and apparatus for managing a controller includes indicating, by a processor of a first device, to the controller of a second device to enter a second power state from a first power state. The controller of the second device responds to the processor of the first device with a confirmation. The processor of the first device transmits a signal to the controller of the second device to enter the second power state. Upon receiving a wake event, the controller of the second device exits the second device from the second power state to the first power state.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: August 27, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Christopher T. Weaver, Indrani Paul, Benjamin Tsien, Mihir Shaileshbhai Doctor, Stephen V. Kosonocky, John P. Petry, Thomas J. Gibney
  • Patent number: 12056535
    Abstract: Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on an integrated circuit (IC), and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: August 6, 2024
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Indrani Paul, Leonardo De Paula Rosa Piga, Mahesh Subramony, Sonu Arora, Donald Cherepacha, Adam N C Clark
  • Publication number: 20240235376
    Abstract: The disclosed voltage regulator circuit includes a capacitor bank configured for a first voltage step corresponding to a voltage undershoot, and a shunt circuit configured for a second voltage step exceeding the first voltage step. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: September 29, 2023
    Publication date: July 11, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: David King Wai Li, Amanullah Samit, Indrani Paul, Meeta Surendramohan Srivastav, Sriram Sambamurthy
  • Patent number: 12001265
    Abstract: Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: June 4, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin Tsien, Alexander J. Branover, Christopher T. Weaver, Indrani Paul, Mihir Shaileshbhai Doctor, John P. Petry, Stephen V. Kosonocky, Thomas J. Gibney, Jose G. Cruz, Pravesh Gupta, Chintan S. Patel
  • Publication number: 20240121192
    Abstract: The disclosed device for packet coalescing includes detecting a trigger condition for initiating packet coalescing of packet traffic and sending, to an endpoint device, a notification to start packet coalescing. The device can observe a status in response to starting the packet coalescing and report a performance of the packet coalescing. A system can include a controller that detects a trigger condition for packet coalescing and notifies an endpoint device via a notification register. The controller can read a status register to report, based on the read status, a packet coalescing performance. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: March 31, 2023
    Publication date: April 11, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ashwini Chandrashekhara Holla, Indrani Paul, Alexander J. Branover, Carlos Javier Moreira
  • Publication number: 20240113914
    Abstract: An apparatus and method for efficiently performing power management for multiple clients of a semiconductor chip that supports remote manageability. In various implementations, a network interface receives a packet, and sends at least an indication of the packet to a manageability processing circuitry (MPC) of a processing node with multiple clients for processing tasks. The MPC determines whether a client or itself is a destination needed to process the packet. If the destination is the MPC, then packet processing is done by the MPC without involvement from the clients, which can be in an idle state. For example, the MPC can process a remote manageability packet requesting diagnostic information from one or more clients of the processing node. The network interface and the MPC use a sideband communication channel for data transmission, which foregoes lane training for further reduction in latency and power consumption.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Sriram Sambamurthy, Indrani Paul, David Boardman Kramer, Madhusudan Chilakam
  • Publication number: 20240085964
    Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Sriram Sambamurthy, Sriram Sundaram, Indrani Paul, Larry David Hewitt, Anil Harwani, Aaron Joseph Grenat, Dana Glenn Lewis, Leonardo Piga, Wonje Choi, Karthik Rao
  • Patent number: 11886878
    Abstract: An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: January 30, 2024
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Sukesh Shenoy, Adam N. C. Clark, Indrani Paul