Patents by Inventor Indranil Palit

Indranil Palit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12151705
    Abstract: A scene creation system for an autonomous vehicle includes one or more controllers executing instructions to receive perception data and map data of a roadway the autonomous vehicle is traveling along, and identify a plurality of lane segments of the roadway that the autonomous vehicle travels along based on the perception data and the map data. The one or more controllers connect the plurality of lane segments together based on a spatial relationship between the plurality of lane segments to create a lane graph. The one or more controllers classify each of the plurality of lane segments of the lane graph to one or more lane attributes and reassemble the plurality of lane segments to create a representation of the roadway. The one or more controllers recreate a scene of an environment surrounding the autonomous vehicle based on the representation of the lanes that are part of the roadway.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: November 26, 2024
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Guangyu Jeff Zou, Brent Navin Roger Bacchus, Michael Alan Losh, Indranil Palit
  • Patent number: 12087062
    Abstract: A method for optimizing sign includes receiving, by a controller of a vehicle, sensor data from a plurality of sensors of the vehicle. The method further includes detecting a sign along a road while the vehicle is in motion using the sensor data and, in response to detecting the sign along the road of the vehicle, determining an optimal location of the vehicle relative to the sign to recognize the sign. Further, the method includes recognizing a content of the sign using an optimal frame captured by the camera at the optimal location and, in response to recognizing the content of the sign, filtering the plurality of frames of the video captured by the camera to minimize a use of a computational resources of the controller.
    Type: Grant
    Filed: April 4, 2023
    Date of Patent: September 10, 2024
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Alireza Esna Ashari Esfahani, Indranil Palit
  • Publication number: 20240253660
    Abstract: A lanelet classification system for an autonomous vehicle includes one or more controllers including a classifier having a neural network that classifies lanelets of a lane graph structure based on one or more lane attributes. In one embodiment, the one or more controllers execute instructions to build the neural network. In another embodiment, the one or more controllers train the neural network to classify each lanelet of the lane graph structure.
    Type: Application
    Filed: January 31, 2023
    Publication date: August 1, 2024
    Inventors: Guangyu Jeff Zou, Brent Navin Roger Bacchus, Michael Alan Losh, Indranil Palit
  • Publication number: 20240246558
    Abstract: A scene creation system for an autonomous vehicle includes one or more controllers executing instructions to receive perception data and map data of a roadway the autonomous vehicle is traveling along, and identify a plurality of lane segments of the roadway that the autonomous vehicle travels along based on the perception data and the map data. The one or more controllers connect the plurality of lane segments together based on a spatial relationship between the plurality of lane segments to create a lane graph. The one or more controllers classify each of the plurality of lane segments of the lane graph to one or more lane attributes and reassemble the plurality of lane segments to create a representation of the roadway. The one or more controllers recreate a scene of an environment surrounding the autonomous vehicle based on the representation of the lanes that are part of the roadway.
    Type: Application
    Filed: January 23, 2023
    Publication date: July 25, 2024
    Inventors: Guangyu Jeff Zou, Brent Navin Roger Bacchus, Michael Alan Losh, Indranil Palit
  • Patent number: 9712146
    Abstract: Various processor architectures for mixed signal computation exploit the unique characteristics of advanced CMOS technologies, such as fin-based, multi-gate field effect transistors, and/or emerging technologies such as tunnel field effect transistors (TFETs). The example processors disclosed herein are cellular neural network (CNN)-inspired and eliminate the need for voltage controlled current sources (VCCSs), which have previously been utilized to realize feedback and feed-forward templates in CNNs and are the dominant source of power consumption in a CNN array. The example processors replace VCCSs with comparators, which can be efficiently realized with TFETs given their high intrinsic gain. Power efficiencies are in the order of 10,000 giga-operations per second per Watt (GOPS/W), which represents an improvement of more than ten times over state-of-the-art architectures seeking to accomplish similar information processing tasks.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: July 18, 2017
    Assignee: University of Notre Dame du Lac
    Inventors: Behnam Sedighi, Michael Niemier, Xiaobo Sharon Hu, Indranil Palit
  • Publication number: 20170085255
    Abstract: Various processor architectures for mixed signal computation exploit the unique characteristics of advanced CMOS technologies, such as fin-based, multi-gate field effect transistors, and/or emerging technologies such as tunnel field effect transistors (TFETs). The example processors disclosed herein are cellular neural network (CNN)-inspired and eliminate the need for voltage controlled current sources (VCCSs), which have previously been utilized to realize feedback and feed-forward templates in CNNs and are the dominant source of power consumption in a CNN array. The example processors replace VCCSs with comparators, which can be efficiently realized with TFETs given their high intrinsic gain. Power efficiencies are in the order of 10,000 giga-operations per second per Watt (GOPS/W), which represents an improvement of more than ten times over state-of-the-art architectures seeking to accomplish similar information processing tasks.
    Type: Application
    Filed: September 18, 2015
    Publication date: March 23, 2017
    Inventors: Behnam Sedighi, Michael Niemier, Xiaobo Sharon Xu, Indranil Palit