Patents by Inventor Indumini Ramuthu

Indumini Ramuthu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Linear switch circuits and methods
    Patent number: 11515870
    Abstract: A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (VDS) saturation condition and controls the first and second power FETs accordingly.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: November 29, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Roland Karl Son, Craig Bennett Greenberg, Indumini Ramuthu
  • LINEAR SWITCH CIRCUITS AND METHODS
    Publication number: 20210242866
    Abstract: A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (VDS) saturation condition and controls the first and second power FETs accordingly.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Inventors: Roland Karl Son, Craig Bennett Greenberg, Indumini Ramuthu