Abstract: A multi-port charging system includes a controller having a power input terminal coupled to a DC power output of a converter, multiple power output terminals coupled to the power input terminal, and a communications input terminal. The system includes multiple charger ports, the respective charger ports having a charging power line coupled to a respective one of the power output terminals, and a communications line coupled to the communications input terminal. The controller is configured to control the state of the control output terminal to set a voltage of the DC power output according to a selected highest common compatible voltage of one or more sink devices coupled to one or more respective ones of the charger ports.

Abstract: A multi-port charging system includes a controller having a power input terminal coupled to a DC power output of a converter, multiple power output terminals coupled to the power input terminal, and a communications input terminal. The system includes multiple charger ports, the respective charger ports having a charging power line coupled to a respective one of the power output terminals, and a communications line coupled to the communications input terminal. The controller is configured to control the state of the control output terminal to set a voltage of the DC power output according to a selected highest common compatible voltage of one or more sink devices coupled to one or more respective ones of the charger ports.

Abstract: In some examples, a circuit includes a state machine. The state machine is configured to operate in a buck state in which the state machine is configured to control a power converter to operate in a buck mode of operation at a first frequency. The state machine is configured to determine that a switch time of the power converter has decreased to within a threshold amount of a minimum switch time for the power converter. The state machine is configured to, responsive to the switch time of the power converter having decreased to within the threshold amount of the minimum switch time for the power converter, transition from the buck state to a reduced frequency buck state in which the state machine is configured to control the power converter to operate in the buck mode of operation at a second frequency that is less than the first frequency.

Abstract: In some examples, a circuit includes a state machine. The state machine is configured to operate in a buck state in which the state machine is configured to control a power converter to operate in a buck mode of operation at a first frequency. The state machine is configured to determine that a switch time of the power converter has decreased to within a threshold amount of a minimum switch time for the power converter. The state machine is configured to, responsive to the switch time of the power converter having decreased to within the threshold amount of the minimum switch time for the power converter, transition from the buck state to a reduced frequency buck state in which the state machine is configured to control the power converter to operate in the buck mode of operation at a second frequency that is less than the first frequency.

Abstract: Back-to-back power field-effect transistors with associated current sensors are disclosed. An example apparatus includes a first power field-effect transistor (FET) having a first source, and a second power FET having a second source. The first and second power FETs share a common drain. The first and second sources positioned on a first side of a substrate and the common drain positioned on a second side of the substrate opposite the first side. The example apparatus includes a current sensing FET positioned between a first portion of the first source of the first power FET and a second portion of the first source of the first power FET. The current sensing FET senses a current passing through the first and second power FETs.

Abstract: A wafer test probe system, probe card, and method to test back-to-back connected first and second transistors of a wafer. The probe card includes a waveform generator circuit and probe needles to couple the waveform generator circuit to provide a first pulse signal of a first polarity using a body diode of the first transistor to test the second transistor, and to provide a second pulse signal of a second polarity using a body diode of the second transistor to the test the first transistor. One example includes a resistor connected between the waveform generator circuit and one of the probe needles. The probe card includes a probe needle to connect a sense transistor of the wafer to the first transistor during wafer probe testing.

Abstract: A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (VDS) saturation condition and controls the first and second power FETs accordingly.

Abstract: A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (VDS) saturation condition and controls the first and second power FETs accordingly.

Abstract: A multi-port charging system includes a controller having a power input terminal coupled to a DC power output of a converter, multiple power output terminals coupled to the power input terminal, and a communications input terminal. The system includes multiple charger ports, the respective charger ports having a charging power line coupled to a respective one of the power output terminals, and a communications line coupled to the communications input terminal. The controller is configured to control the state of the control output terminal to set a voltage of the DC power output according to a selected highest common compatible voltage of one or more sink devices coupled to one or more respective ones of the charger ports.

Abstract: A wafer test probe system, probe card, and method to test back-to-back connected first and second transistors of a wafer. The probe card includes a waveform generator circuit and probe needles to couple the waveform generator circuit to provide a first pulse signal of a first polarity using a body diode of the first transistor to test the second transistor, and to provide a second pulse signal of a second polarity using a body diode of the second transistor to the test the first transistor. One example includes a resistor connected between the waveform generator circuit and one of the probe needles. The probe card includes a probe needle to connect a sense transistor of the wafer to the first transistor during wafer probe testing.

Abstract: Back-to-back power field-effect transistors with associated current sensors are disclosed. An example apparatus includes a first power field-effect transistor (FET) having a first source, and a second power FET having a second source. The first and second power FETs share a common drain. The first and second sources positioned on a first side of a substrate and the common drain positioned on a second side of the substrate opposite the first side. The example apparatus includes a current sensing FET positioned between a first portion of the first source of the first power FET and a second portion of the first source of the first power FET. The current sensing FET senses a current passing through the first and second power FETs.

Abstract: Techniques are described for integrating power field-effect transistors (FETs), pre-drivers, controllers, and/or resistors into a common multi-chip package for implementing multi-phase bridge circuits. The techniques may provide a multi-chip package with at least two high-side (HS) FETs and at least two low-side (LS) FETs, and place the at least two HS FETs or the at least LS FETs on a common die. Placing at least two FETs on a common die may reduce the number of die and the number of thermal pads (i.e., die pads) needed to implement a set of power FETs, thereby decreasing component count of a multi-phase bridge circuit and/or allowing a more compact, higher current density multi-phase bridge circuit to be obtained without significantly increasing thermal power dissipation of the circuit.

Abstract: Techniques are described for integrating power field-effect transistors (FETs), pre-drivers, controllers, and/or resistors into a common multi-chip package for implementing multi-phase bridge circuits. The techniques may provide a multi-chip package with at least two high-side (HS) FETs and at least two low-side (LS) FETs, and place the at least two HS FETs or the at least LS FETs on a common die. Placing at least two FETs on a common die may reduce the number of die and the number of thermal pads (i.e., die pads) needed to implement a set of power FETs, thereby decreasing component count of a multi-phase bridge circuit and/or allowing a more compact, higher current density multi-phase bridge circuit to be obtained without significantly increasing thermal power dissipation of the circuit.

Abstract: Techniques are described for integrating power field-effect transistors (FETs), pre-drivers, controllers, and/or resistors into a common multi-chip package for implementing multi-phase bridge circuits. The techniques may provide a multi-chip package with at least two high-side (HS) FETs and at least two low-side (LS) FETs, and place the at least two HS FETs or the at least LS FETs on a common die. Placing at least two FETs on a common die may reduce the number of die and the number of thermal pads (i.e., die pads) needed to implement a set of power FETs, thereby decreasing component count of a multi-phase bridge circuit and/or allowing a more compact, higher current density multi-phase bridge circuit to be obtained without significantly increasing thermal power dissipation of the circuit.

Abstract: Various apparatuses, methods and systems for damping a current driver are disclosed herein. For example, some embodiments provide an apparatus for supplying current, including an output transistor connected between a voltage supply and a current output, and an active clamp connected between the current output and a current sink. The active clamp is adapted to connect the current output to the current sink when a voltage at the current output reaches a predetermined state relative to a voltage at a control input of the output transistor.

Abstract: An optical disk drive system associated with a laser diode is described. The optical disk drive system comprises a current generator for receiving input signals; a current switch coupled to receive timing signals; a current driver coupled to receive output signals from the current switch and the current generator, the current driver further comprising a driver with wave shape control selected from the group consisting of a laser diode read driver and a laser diode write driver, wherein the driver with shape control is operative for transmitting at least one output signal that is a scaled version of at least one of the output signals received from the current generator, wherein the current driver is operative for transmitting at least one output signal driving the laser diode.

Abstract: A high frequency modulator is described. It comprises: a first converter for receiving a constant current signal and transmitting a first converted signal; an adder coupled the first converter and operative for transmitting a summed signal in response to receiving the first converted signal and selectively receiving a triangular signal; a first oscillator coupled to the adder for receiving the summed signal, the first oscillator operative for transmitting a time varying current signal; a second converter coupled to the first oscillator for receiving the time varying current signal and operative for transmitting a second converted signal; and an output device selectively coupled to the second converter and operative for transmitting an output signal in response to receiving either the second converted signal or an offset signal.

Abstract: Various apparatuses, methods and systems for damping a current driver are disclosed herein. For example, some embodiments provide an apparatus for supplying current, including an output transistor connected between a voltage supply and a current output, and an active clamp connected between the current output and a current sink. The active clamp is adapted to connect the current output to the current sink when a voltage at the current output reaches a predetermined state relative to a voltage at a control input of the output transistor.

Abstract: A preamplifier and method writes data synchronized with the passing of a write head in a magnetic storage device over bit islands in discrete patterned recording media. The preamplifier contains a write pre-driver that conditions write data, a synchronization circuit that accepts a delay offset value and a write clock and produces a delayed clock, and a write output driver that is gated by the delayed clock to produce write pulses for magnetizing the bit islands. Gating the write output driver using the delayed clock results in more accurate synchronization than delaying the write data into the preamplifier due to the reduction of the overall length and variability of interconnects and transistors in the intervening circuitry.

Abstract: Laser diode driver architectures are disclosed. Some example current drivers are described, including a current channel to provide an output current. The current channel includes a current mirror with emitter degeneration, a startup transistor coupled to the current mirror to generate a DC bias on the current mirror, a beta helper circuit coupled to the current mirror and the startup transistor, to maintain the DC bias on the current mirror, and a cutoff transistor coupled to an emitter terminal of a current mirror transistor and to a reference voltage, to selectively couple the emitter terminal to the reference voltage to conduct the pre-determined output current. The example current drivers also include an output stage coupled to the output of the current mirror and to an output device, wherein the output stage provides a current gain in response to the cutoff transistor coupling the emitter terminal to the reference voltage.