Abstract: An embodiment relates to an integrated circuit comprising at least two electrical connections and at least one coil arranged adjacent to at least one of the electrical connection, wherein the at least one coil each comprises at least one winding and wherein the at least one coil is arranged on or in the integrated circuit.

Abstract: A switching power converter includes an inductor coupled to a terminal operably supplied with an input voltage. A semiconductor switch is coupled to the inductor and configured to enable and disable an input current passing through the inductor in accordance with a drive signal. A current sense circuit is coupled to the inductor or the semiconductor switch and is configured to generate a current sense signal representing the input current passing through the inductor or the semiconductor switch. A control circuit receives the current sense signal and is configured to: close the semiconductor switch regularly in accordance with a clock frequency, to integrate the current sense signal thus providing an integrated current sense signal to compare the integrated current sense signal with a threshold that is a function of the input voltage.

Abstract: A semiconductor device includes a first semiconductor power chip mounted over a first carrier and a second semiconductor power chip mounted over a second carrier. The semiconductor device further includes a contact clip mounted over the first semiconductor power chip and on the second semiconductor power chip. A semiconductor logic chip is mounted over the contact clip.

Abstract: A power converter circuit includes an input and an output. A supply circuit is configured to receive an input signal from the input and to generate a number of supply signals from the input signal. A number of converter units are provided. Each of the plurality of converter units is configured to receive one of the plurality of supply signals and to output an output signal to the output.

Abstract: A semiconductor package includes a base, a die attached to the base, a lead and a connector electrically connecting the lead to the die. A mold compound encapsulates the die, the connector, at least part of the base, and part of the lead, so that the lead extends outward from the mold compound. An electrical insulation layer separate from the mold compound is attached to a surface of the mold compound over the connector. The electrical insulation layer has a fixed, defined thickness so that the package has a guaranteed minimum spacing between an apex of the connector and a surface of the electrical insulation layer facing away from the connector.

Abstract: A circuit arrangement including a rectifier circuit and a current determining circuit. The rectifier circuit is configured to rectify an alternating signal into a rectified signal. The current determining circuit is configured to determine a current of the alternating signal from at least a current of the rectified signal.

Abstract: A signal transmission arrangement includes a transformer with a first and a second winding. A damping circuit has an input terminal for receiving an input signal. The damping circuit is coupled to the first winding and is configured to have an electrical resistance that is dependent on the input signal. An oscillator circuit includes the second winding and is configured to provide an oscillating signal. An evaluation circuit is configured to receive the oscillating signal and to provide an output signal that is dependent on an amplitude of the oscillating signal.

Abstract: A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone.

Abstract: A voltage converter includes a first converter stage including a unipolar transistor coupled to a first inductive storage element, where the first converter stage is configured to provide a first output power signal including a first output current. Also, the voltage converter includes a second converter stage including a bipolar transistor coupled to a second inductive storage element, where the second converter stage is configured to provide a second output power including a second output current, and where a third output current is a sum of the first output current and the second output current. Additionally, the voltage converter includes a control circuit configured to control a power converter including the first output current and the second output current, where the first output current is higher than the second output current when the third output current has a first range of output current.

Abstract: Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.

Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.

Abstract: A circuit arrangement, includes output terminals that provide an output current and input terminals that receive a source current and a source voltage from a DC current source. A maximum power point tracker is coupled between the input terminals and the output terminals and a bypass circuit is coupled between the input terminals and the output terminals. The bypass circuit is configured to enter a bypass state dependent on the output current and dependent on the source current. The source current flows through the bypass circuit in the bypass state.

Abstract: A semiconductor device includes a semiconductor substrate having a main horizontal surface, a back surface arranged opposite the main horizontal surface, a vertical transistor structure including a doped region and a control electrode arranged next to the main horizontal surface, an insulating region arranged at or close to the back surface, a deep vertical trench extending from the main horizontal surface through the semiconductor substrate and to the insulating region, an insulating layer arranged on a side wall of the deep vertical trench, and a low ohmic current path extending at least partially along the insulating layer and between the main horizontal surface and the back surface. A first metallization is in ohmic contact with the doped region and arranged on the main horizontal surface. A control metallization is arranged on the back surface and in ohmic contact with the control electrode via the low ohmic current path.

Abstract: One aspect related to a system configured to split a processed semiconductor wafer. The semiconductor wafer comprises a brittle material and has at least one layer formed on a first surface of the semiconductor wafer. At least one trench is etched in the first surface and through the at least one layer thereby forming a line on the surface where at least some of the brittle material is removed. Provided are means for splitting the semiconductor wafer into separate pieces along the line.

Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity.

Abstract: A method for operating a fluorescent lamp which is connected to a series resonant circuit with a resonant circuit inductance and a resonant circuit capacitance. The method includes applying an excitation AC voltage at an excitation frequency to the series resonant circuit using a half bridge circuit, which has an output to which the series resonant circuit is coupled, and which has a first and a second switch which are alternately switched on and off on the basis of a frequency signal. A current flowing through the resonant circuit is monitored for the presence of a critical operating state. The switched-on times of the first and second switches are shortened in comparison to switched-on times which are predetermined by the frequency signal, upon detection of a critical operating state.

Abstract: A semiconductor including a lateral HEMT and to a method for production of a lateral HEMT is disclosed. In one embodiment, the lateral HEMT has a substrate and a first layer, wherein the first layer has a semiconductor material of a first conduction type and is arranged at least partially on the substrate. Furthermore, the lateral HEMT has a second layer, wherein the second layer has a semiconductor material and is arranged at least partially on the first layer. In addition, the lateral HEMT has a third layer, wherein the third layer has a semiconductor material of a second conduction type, which is complementary to the first conduction type, and is arranged at least partially in the first layer.

Abstract: In one embodiment, a light dimming module is disclosed. The light dimming module has a dimming engine coupled to a digital input interface and an output interface. The dimming engine is configured to provide a N-segment piecewise linear exponential digital control signal, and the output interface is configured to control the intensity of a light source.

Abstract: A method for producing a semiconductor includes providing a p-doped semiconductor body having a first side and a second side; implanting protons into the semiconductor body via the first side to a target depth of the semiconductor body; bonding the first side of the semiconductor body to a carrier substrate; forming an n-doped zone in the semiconductor body by heating the semiconductor body such that a pn junction arises in the semiconductor body; and removing the second side of the semiconductor body at least as far as a space charge zone spanned at the pn junction.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is formed on the horizontal surface. An epitaxial region is formed by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask. The epitaxial region is polished by a chemical-mechanical polishing process stopping on the epitaxy hard mask. A vertical trench is formed in the semiconductor body. An insulated field plate is formed in a lower portion of the vertical trench and an insulated gate electrode is formed above the insulated field plate. Further, a method for forming a field-effect semiconductor device is provided.