Abstract: Structures for reducing relative stress between HDP layer and passivation layer are proposed by the invention, where the HDP layer is formed by high density plasma and the passivation layer is a conventional passivation layer. The invention provides some structures that can be divided into two categories: one, a low stress passivation layer is directly formed on a HDP layer; another, a low stress layer is formed between passivation layer and HDP layer to reduce relative layer that between any two adjacent layers. Therefore, it is crystal-clear that possible structures of the invention comprise following varieties: First, a low stress passivation layer is located between a passivation layer and a HDP layer. Second, a lower stress passivation layer directly locates on a HDP layer. Third, a low stress layer is formed between a passivation layer and a HDP layer.

Abstract: Structures for reducing relative stress between HDP layer and passivation layer are proposed by the invention, where the HDP layer is formed by high density plasma and the passivation layer is a conventional passivation layer. The invention provides some structures that can be divided into two categories: one, a low stress passivation layer is directly formed on a HDP layer; another, a low stress layer is formed between passivation layer and HDP layer to reduce relative layer that between any two adjacent layers. Therefore, it is crystal-clear that possible structures of the invention comprise following varieties: First, a low stress passivation layer is located between a passivation layer and a HDP layer. Second, a lower stress passivation layer directly locates on a HDP layer. Third, a low stress layer is formed between a passivation layer and a HDP layer.

Abstract: Structures for reducing relative stress between HDP layer and passivation layer are proposed by the invention, where the HDP layer is formed by high density plasma and the passivation layer is a conventional passivation layer. The invention provides some structures that can be divided into two categories: one, a low stress passivation layer is directly formed on a HDP layer; another, a low stress layer is formed between passivation layer and HDP layer to reduce relative layer that between any two adjacent layers. Therefore, it is crystal-clear that possible structures of the invention comprise following varieties: First, a low stress passivation layer is located between a passivation layer and a HDP layer. Second, a lower stress passivation layer directly locates on a HDP layer. Third, a low stress layer is formed between a passivation layer and a HDP layer.

Abstract: An apparatus for detecting the position of a collimator in a sputter-processing chamber is disclosed in the present invention. A target holder is at the upper portion of the chamber and a target is attached to the bottom surface of the target holder. A substrate holder is at the underlying portion of the chamber and it is opposed to the target holder. A silicon wafer is putted on the substrate holder. Two supporters are on an inner surface of the housing of the chamber and are separated to oppose to each other, the supporters protrude the housing. A collimator is putted on the supporters and it is parallel to the surface of the target. Two sensors is attached on the under surface or the lateral surface of the supporters. The horizontal height of the sensors is lower than that of the collimator. When the collimator is heated and it distorts, the position of the collimator will change to enter into the available area of the sensors.

Abstract: The present invention provides a method of forming a dielectric layer on a semiconductor wafer. The semiconductor wafer comprises a bottom dielectric layer and a plurality of metal lines each having a rectangular cross section positioned on the bottom dielectric layer. The method is performed in a high-density plasma chemical vapor deposition apparatus. A first deposition process at a first etching/deposition (E/D) ratio is performed to form a first dielectric layer with a predetermined thickness on the semiconductor wafer. The first dielectric layer covers the surface of the metal lines and forms a triangular ridge above each metal line. The upper side of each of the ridges has two slanted side-walls. Then, a second deposition process at a second E/D ratio is performed to form a second dielectric layer with a predetermined thickness on the semiconductor wafer with the second deposition process etching rate being near zero.