Abstract: The present invention relates to an event driven digital signal processor 1 comprising: a central arithmetical unit 5, a register 4, a controller 3, an instruction memory 2, and input/output devices. The instruction memory 2 is arranged to include time performance constraints and events. An event control unit 6 is arranged to recognize an event and to control processing to be carried out as a consequence of the event while fulfilling the time performance constraints. The controller 3 is arranged to suspend processing of the time performance constraints after initiating operations in the event control unit 6. The controller 3 resumes processing when advised by the event control unit 6.

Abstract: The present invention relates to an event driven digital signal processor 1 comprising: a central arithmetical unit 5, a register 4, a controller 3, an instruction memory 2, and input/output devices. The instruction memory 2 is arranged to include time performance constraints and events. An event control unit 6 is arranged to recognize an event and to control processing to be carried out as a consequence of the event while fulfilling the time performance constraints. The controller 3 is arranged to suspend processing of the time performance constraints after initiating operations in the event control unit 6.

Abstract: A memory structure for storing memory vectors in at least one storage location. A plurality of storage locations store memory vectors. After configuration each storage location has a length adapted to a length of a memory vector stored therein. The storage locations are arranged parallel to each other and extend from a memory input deeper into the memory such that each memory vector is arranged to be undividedly stored in sequential order with a beginning of a vector at the memory input. Storage place addressing is made to the memory input. Input buffers are arranged to input the memory vectors in unbroken sequence according to the addressing. The vectors are inputted in a buffer-by-buffer manner. Output buffers are arranged to output the memory vectors in unbroken sequence according to the addressing in a buffer-by-buffer manner.

Abstract: The invention relates to a new memory structure specially adapted for the storage of memory vectors. Each of the storage positions (#1, Mi-#M, Mi) of the memory has a length adapted to the length of large vectors and is parallelly arranged extending from an input and/or output for information and deeper into the memory. In this way each vector is stored undivided in a sequential order with the beginning of the vector at the input and/or output of the memory (memory field F1 in memory plane Mi). Addressing is made to the input and/or output of the memory. There are means (1IB-MIB, 1UB-MUB) acting like shift registers for the inputting and outputting of information in undivided sequence to/from the storage positions in the memory.

Abstract: A method for increasing a working speed in a synchronous digital system, which includes a plurality of separate system parts, and for permitting communication between at least two of the system parts. A common reference signal having a reference frequency is distributed to all system parts. An internal signal clock oscillator of each system part is phase locked to the reference signal. Data is communicated between the at least two system parts by relating the reference signal with the internal clock signal of each of the two system parts by adjusting a phase position of the internal clock signal of a second of the two system parts dependent upon a time delay of the data communicated from the first system part to the second system part so that the phase positions of the internal clock signals correspond.