Abstract: An integrated, planar, single-channel, photodetector-amplifier device is disclosed. The single-channel device includes a photodetector layer and an amplifier layer above the photodetector layer. The photodetector layer is low-doped to give a low dark current and is sufficiently thick to give a high quantum efficiency. The amplifier layer is of a smaller thickness and is a more highly doped material than the photodetector layer, to provide an amplifier having high gain. An insulating layer is included between the photodetector and amplifier layers for electrically isolating the photodetector and amplifier layers. The layers are fabricated on a substrate. Isolation regions are also included for electrically laterally isolating a photodetector, amplifier, and other circuit components comprising the single channel device from each other.

Abstract: An adaptive analog processor incorporating a analog shift register having a plurality of taps, multipliers at each tap for multiplying the tap value times a weight value, a first adder for summing the output of the multipliers, a second adder for subtracting the output of the adder from a second analog signal, means for incrementing the weights in response to the magnitude and polarity of the error signal and the polarity of the data signal. The invention overcomes the problem of building monolithic multitap adaptive filters utilizing the clipped-data least mean square error algorithm.

Abstract: A charge control circuit for bidirectionally transferring metered amounts of charge, selectively, through a transfer channel of a four gate electrode charge coupled device (CCD) is disclosed. The bidirectional charge control circuit is used primarily to increment and decrement metered amounts of charge respectively to and from a charge storage medium. More specifically, five electrical signals are generated to have varying potentials in accordance with predetermined time sequences. These signals are applied to the four gate electrode CCD in a selected one of two states to either increment or decrement a metered amount of charge therethrough to or from the charge storage medium respectively, in a predetermined number of five segments. One of the generated signals governs the metering of charge for each increment or decrement operation.

Abstract: A coherent sampled CMOS readout circuit and signal processor coupled to a CCD shift register operated by a two-phase minority carrier transfer clock system. The invention comprises a multiplex MIS switch, a reverse biased collection diode, an N channel MOSFET reset switch, a P channel MOSFET electrometer amplifier, and a sample and hold circuit, the configuration having four distinct operational timing subintervals within a clock period wherein the charge is shifted from one shift register bit to another and finally to the output bit. This removes the Nyquist noise associated with the reset switch, suppresses switching transients and 1/f surface noise to thereby improve the signal to noise ratio, i.e., dynamic range, for a CCD array and readout system.