Abstract: A semiconductor device includes a barrier region and a channel region, source and drain electrodes, and a gate structure that is configured to control a conductive connection between the source and drain electrodes, wherein the barrier region comprises a first barrier layer and a second barrier layer, wherein in a central portion of the device the second barrier layer is the only layer that is disposed over the channel region, wherein in outer lateral portions of the device the first barrier layer is disposed over the channel region, wherein the first and second barrier layers are each III-V semiconductor alloys, and wherein a molar fraction of a second type III element in the central portion is higher than a molar fraction of the second type III element in the first barrier layer.

Abstract: A semiconductor device includes a semiconductor substrate including a barrier region, a channel layer disposed below the barrier region and forming a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel layer near the heterojunction, and a sub-channel region disposed below the channel layer, and a first interface in the semiconductor substrate between a first region of type III-V material and a second region of type III-V material that is disposed below the first region of type III-V material, wherein the first and second regions of type III-V material form polarization charges on either side of the first interface, wherein the first interface is within or formed by the sub-channel region, and wherein semiconductor substrate has a vertically varying dopant concentration of deep energy acceptor dopant atoms that is locally increased at the first interface.

Abstract: A semiconductor device includes a semiconductor substrate including a barrier region, a channel layer disposed below the barrier region and forming a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel layer near the heterojunction, and a sub-channel region disposed below the channel layer, and a first interface in the semiconductor substrate between a first region of type III-V material and a second region of type III-V material that is disposed below the first region of type III-V material, wherein the first and second regions of type III-V material form polarization charges on either side of the first interface, wherein the first interface is within or formed by the sub-channel region, and wherein semiconductor substrate has a vertically varying dopant concentration of deep energy acceptor dopant atoms that is locally increased at the first interface.

Abstract: A method includes forming a silicon substrate including first and second substrate layers, the first substrate layer extending to the rear surface, the second substrate layer extending to a first side of the silicon substrate that is opposite from the rear surface such that the first substrate layer is completely separated from the first side by the second substrate layer, forming a nucleation region on the first side of the silicon substrate, the nucleation region including a nitride layer, forming a lattice transition layer on the nucleation region, the lattice transition layer being configured to alleviate stress arising in the silicon substrate due to lattice mismatch between the silicon substrate and other layers in the compound semiconductor device structure, and epitaxially growing a type III-V semiconductor nitride region on the lattice transition layer.

Abstract: A compound semiconductor device structure having a main surface and a rear surface includes a silicon substrate including first and second substrate layers. The first substrate layer extends to the rear surface. The second substrate layer extends to a first side of the substrate that is opposite from the rear surface such that the first substrate layer is completely separated from the first side by the second substrate layer. A nucleation region is formed on the first side of the silicon substrate and includes a nitride layer. A lattice transition layer is formed on the nucleation region and includes a type III-V semiconductor nitride. The lattice transition layer is configured to alleviate stress arising in the silicon substrate due to lattice mismatch between the silicon substrate and other layers in the compound semiconductor device structure. The second substrate layer is configured to suppress an inversion layer in the silicon substrate.

Abstract: A compound semiconductor device structure having a main surface and a rear surface includes a silicon substrate including first and second substrate layers. The first substrate layer extends to the rear surface. The second substrate layer extends to a first side of the substrate that is opposite from the rear surface such that the first substrate layer is completely separated from the first side by the second substrate layer. A nucleation region is formed on the first side of the silicon substrate and includes a nitride layer. A lattice transition layer is formed on the nucleation region and includes a type III-V semiconductor nitride. The lattice transition layer is configured to alleviate stress arising in the silicon substrate due to lattice mismatch between the silicon substrate and other layers in the compound semiconductor device structure. The second substrate layer is configured to suppress an inversion layer in the silicon substrate.

Abstract: An electrical circuit includes at least two unit cells configured on a planar substrate which extends in one plane. The unit cells respectively have at least two contact points with a different function and include at least one dielectric layer disposed on the substrate and/or on the unit cells and at least two contact surfaces which are disposed parallel to the plane above the contact points and/or the substrate. The contact points with the same function are connected electrically to at least one common contact surface for at least a part of the contact points of the same function via at least one through-contacting through the dielectric layer and able to be contacted in common from outside via the corresponding contact surfaces.

Abstract: An electronic component includes a printed conductor structure on a substrate, as well as a film which contacts the printed conductor structure. The film has a smaller layer thickness than the printed conductor. The printed conductor structure has a region which is covered by the film for the purpose of contacting.

Abstract: An electronic component has at least one contact surface situated in a contact plane, at least one insulating layer disposed above the contact plane, at least one stabilizing layer disposed on the insulating layer for increasing a mechanical stability of the component, and at least one of a bonding contact and a soldering contact. The insulating layer and the stabilizing layer have at least one opening which opens in an upper side of the stabilizing layer. The upper side of the stabilizing layer is oriented away from the contact surface. The opening extends through the stabilizing layer and the insulating layer as far as the contact surface. The at least one of a bonding contact and a soldering contact extends over the stabilizing layer and touches the contact surface through the opening.

Abstract: An electronic component includes a printed conductor structure on a substrate, as well as a film which contacts the printed conductor structure. The film has a smaller layer thickness than the printed conductor. The printed conductor structure has a region which is covered by the film for the purpose of contacting.

Abstract: A semiconductor actuator includes a substrate base, a bending structure which is connected to the substrate base and can be deflected at least partially relative to the substrate base. The bending structure has semiconductor compounds on the basis of nitrides of main group III elements and at least two electrical supply contacts which impress an electrical current in or for applying an electrical voltage to the bending structure. At least two of the supply contacts are disposed at a spacing from each other respectively on the bending structure and/or integrated in the latter.

Abstract: An electrical circuit includes at least two unit cells configured on a planar substrate which extends in one plane. The unit cells respectively have at least two contact points with a different function and include at least one dielectric layer disposed on the substrate and/or on the unit cells and at least two contact surfaces which are disposed parallel to the plane above the contact points and/or the substrate. The contact points with the same function are connected electrically to at least one common contact surface for at least a part of the contact points of the same function via at least one through-contacting through the dielectric layer and able to be contacted in common from outside via the corresponding contact surfaces.

Abstract: A semiconductor component includes a substrate, at least one oblong first electrode disposed on the substrate and at least one second electrode disposed on the substrate. The first and/or the second electrode respectively are closed in its longitudinal direction.

Abstract: A semiconductor actuator includes a substrate base, a bending structure which is connected to the substrate base and can be deflected at least partially relative to the substrate base. The bending structure has semiconductor compounds on the basis of nitrides of main group III elements and at least two electrical supply contacts which impress an electrical current in or for applying an electrical voltage to the bending structure. At least two of the supply contacts are disposed at a spacing from each other respectively on the bending structure and/or integrated in the latter.

Abstract: The present invention relates to a sensor element which has a semiconductor structure based on a Group III-nitride. The semiconductor sensor element serves for determining the pressure, the temperature, a force, a deflection or an acceleration. It has a substrate base 1, disposed thereon, a homogeneous semiconductor layer based on a Group III-nitride, the surface of the homogeneous semiconductor layer 2 orientated towards the substrate base 1 having at least partially a spacing from the surface of the substrate base orientated towards the homogeneous semiconductor layer 2, 2f, and being distinguished in that at least two electrical conducting contacts 5 for conducting an electrical output signal, which can be generated by the homogeneous semiconductor layer 2, 2f, are disposed on, at or under the homogeneous semiconductor layer 2, 2f or are integrated in the latter.

Abstract: The present invention relates to a field effect transistor having heterostructure with a buffer layer or substrate. A channel is arranged on the buffer layer or on the substrate, and a capping layer is arranged on the channel. The channel consists of a piezopolar material and either the region around the boundary interface between the buffer layer or substrate and channel or the region around the boundary interface between the channel and capping layer is doped in a manner such that the piezocharges occurring at the respective boundary interface are compensated.

Abstract: The present invention relates to a field effect transistor having heterostructure with a buffer layer or substrate. A channel is arranged on the buffer layer or on the substrate, and a capping layer is arranged on the channel. The channel consists of a piezopolar material and either the region around the boundary interface between the buffer layer or substrate and channel or the region around the boundary interface between the channel and capping layer is doped in a manner such that the piezocharges occurring at the respective boundary interface are compensated.

Abstract: The present invention relates to a sensor element which has a semiconductor structure based on a Group III-nitride. The semiconductor sensor element serves for determining the pressure, the temperature, a force, a deflection or an acceleration. It has a substrate base 1, disposed thereon, a homogeneous semiconductor layer based on a Group III-nitride, the surface of the homogeneous semiconductor layer 2 orientated towards the substrate base 1 having at least partially a spacing from the surface of the substrate base orientated towards the homogeneous semiconductor layer 2, 2f, and being distinguished in that at least two electrical conducting contacts 5 for conducting an electrical output signal, which can be generated by the homogeneous semiconductor layer 2, 2f, are disposed on, at or under the homogeneous semiconductor layer 2, 2f or are integrated in the latter.

Abstract: The present invention relates to a field effect transistor having heterostructure with a buffer layer or substrate. A channel is arranged on the buffer layer or on the substrate, and a capping layer is arranged on the channel. The channel consists of a piezopolar material and either the region around the boundary interface between the buffer layer or substrate and channel or the region around the boundary interface between the channel and capping layer is doped in a manner such that the piezocharges occurring at the respective boundary interface are compensated.

Abstract: The invention relates to a heterostructure with a buffer layer or substrate, a channel arranged on the buffer layer or substrate and a capping layer arranged on the channel. Said channel is made from a piezopolar material and either the region around the boundary interface between the buffer layer or substrate and the channel, or the region around the boundary interface between the channel and the capping layer is doped in such a way that any piezo charging which occurs at the respective boundary interface is compensated.