Abstract: An oscillator, a transmission/reception device for a bus system, and a method for generating a clock frequency with the oscillator are indicated. The oscillator serves to generate a clock frequency and includes a timing element that has a frequency-determining capacitance for determining the frequency of the clock frequency, and a comparator, the comparator being configured to detect a threshold voltage to which the frequency-determining capacitance is to be charged, and the comparator having a switchable capacitance for offset compensation.

Abstract: A subscriber station for a bus system and a method for reducing line-related emissions in a bus system are provided. The subscriber station includes an edge controller for symmetrizing switching edges in the bus system. The edge controller includes an element for generating a setpoint voltage characteristic on a bus in the bus system and a current mirror for transmitting the generated setpoint voltage characteristic to the bus.

Abstract: A user station for a bus system and a method for reducing line-conducted emissions in a bus system, in which the user station includes a transceiver for transmitting or receiving a message from at least one additional user station of the bus system via the bus system. In the bus system, exclusive, collision-free access to a bus of the bus system by a user station is at least temporarily ensured. The transceiver includes an emission control device for controlling the properties of the transceiver to reduce line-conducted emissions in the bus system. The transceiver is also configured for switching the emission control device on or off as a function of the arbitration phase and the data area of the message.

Abstract: A subscriber station for a bus system and a method for reducing line-conducted emissions in a bus system are provided. The subscriber station includes a first delay element for delaying a signal of a bus of the bus system and a second delay element for delaying a signal of a bus of the bus system, the delay time of the first and second delay element being capable of being digitally set as a function of the bus state or independently for rising and falling signal edges at the bus of the bus system in order to carry out a signal symmetrization during the rising and falling signal edge at the bus.

Abstract: A user station for a bus system and a method for improving the transmission quality in a bus system are provided. The user station includes a transceiver for transmitting or receiving a message to/from at least one additional user station of the bus system via the bus system. In the bus system, exclusive, collision-free access to a bus of the bus system by a user station is at least temporarily ensured. The transceiver includes a transmission signal processing device for transmission signal processing of a transmission signal to be transmitted by the transceiver. The transmission signal processing device is configured for setting a predetermined bit symmetry of bits of the transmission signal by generating an internal transmission signal for the message. In the internal transmission signal, the dominant phase of the bits is shortened and the recessive phase of the bits is lengthened.

Abstract: An oscillator, a transmission/reception device for a bus system, and a method for generating a clock frequency with the oscillator are indicated. The oscillator serves to generate a clock frequency and includes a timing element that has a frequency-determining capacitance for determining the frequency of the clock frequency, and a comparator, the comparator being configured to detect a threshold voltage to which the frequency-determining capacitance is to be charged, and the comparator having a switchable capacitance for offset compensation.

Abstract: A user station for a bus system and a method for improving the transmission quality in a bus system are provided. The user station includes a transceiver for transmitting or receiving a message to/from at least one additional user station of the bus system via the bus system. In the bus system, exclusive, collision-free access to a bus of the bus system by a user station is at least temporarily ensured. The transceiver includes a transmission signal processing device for transmission signal processing of a transmission signal to be transmitted by the transceiver. The transmission signal processing device is configured for setting a predetermined bit symmetry of bits of the transmission signal by generating an internal transmission signal for the message. In the internal transmission signal, the dominant phase of the bits is shortened and the recessive phase of the bits is lengthened.

Abstract: A user station for a bus system and a method for reducing line-conducted emissions in a bus system, in which the user station includes a transceiver for transmitting or receiving a message from at least one additional user station of the bus system via the bus system. In the bus system, exclusive, collision-free access to a bus of the bus system by a user station is at least temporarily ensured. The transceiver includes an emission control device for controlling the properties of the transceiver to reduce line-conducted emissions in the bus system. The transceiver is also configured for switching the emission control device on or off as a function of the arbitration phase and the data area of the message.

Abstract: A subscriber station for a bus system and a method for reducing line-conducted emissions in a bus system are provided. The subscriber station includes a first delay element for delaying a signal of a bus of the bus system and a second delay element for delaying a signal of a bus of the bus system, the delay time of the first and second delay element being capable of being digitally set as a function of the bus state or independently for rising and falling signal edges at the bus of the bus system in order to carry out a signal symmetrization during the rising and falling signal edge at the bus.

Abstract: A subscriber station for a bus system and a method for reducing line-related emissions in a bus system are provided. The subscriber station includes an edge controller for symmetrizing switching edges in the bus system. The edge controller includes an element for generating a setpoint voltage characteristic on a bus in the bus system and a current mirror for transmitting the generated setpoint voltage characteristic to the bus.

Abstract: An integrated electronic device includes circuitry for providing a regulated output supply voltage level at an output node from an adjustable current. The circuitry includes an adjustable current source for providing the adjustable current and for adjusting the adjustable current to a magnitude of a target value in response to a configuration signal, an auxiliary adjustable current source providing an auxiliary adjustable current having a magnitude corresponding to the target value, and an output supply voltage level regulating loop coupled to the output node and adapted to keep the output supply voltage level at a preset value. A current selecting stage is adapted to receive the adjustable current and the auxiliary current. The current selecting stage is further adapted to supply a selected current corresponding to a lesser value of the adjustable current and the auxiliary adjustable current.

Abstract: The present invention provides a radiation sensor featuring a plurality of individual sensor elements, e.g. pixels, each of which having a radiation detection portion that is adapted to generate an electric current in response to impingement of electromagnetic radiation and a current amplifier for amplifying the photoelectric current generated by the radiation detection portion. Current amplification is therefore performed locally within each pixel of the radiation sensor itself. This local current amplification effectively allows to increase sensitivity and response of the radiation sensor and therefore enables implementation of the radiation sensor on the basis of CMOS technology.

Abstract: An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current generating stage comprises a crude bias current generator for generating an crude bias current during a power up phase in which at least one of the multiple supply voltages has not yet reached its target supply voltage level, a reference current stage for providing a reference current having a target current value greater than the target value of the crude bias current when the multiple supply voltages have reached their target supply voltage levels. The maximum current selection stage is adapted to continuously output a bias current which is the maximum current of the crude bias current and the reference current.

Abstract: An electronic device comprising circuitry for providing a Power-on-Reset (POR) signal as a function of a supply voltage level of the circuitry. The circuitry comprises a Vbe-cell or a Vgs-cell comprising a first current path including a first transistor and a second current path including a second transistor. Each transistor has a control terminal for controlling a first current in the first current path and a second current in the second current path, wherein a control voltage level is commonly applied to the control terminals of the first and the second transistor. The control voltage level is derived from the current supply voltage level of the circuitry, and the circuitry further comprises a POR output node for providing a POR output signal, which changes from a first state to a second state in response to the ratio of the magnitudes of the first current and the second current.

Abstract: An integrated electronic device includes a sample and hold stage. The sample and hold stage has a sampling capacitor (C) for an input voltage at an input node (Vin), a first switch (S1) coupled between the input node (Vin) and the sampling capacitor (C) for connecting the input node (Vin) to the sampling capacitor (C). There is also a voltage follower with an input coupled to the sampling capacitor (C). The first switch (S1) includes a first MOS transistor (NM1) coupled between the input node (Vin) and the sampling capacitor (C). The first MOS transistor has a bulk. The sample and hold stage is adapted to selectively couple the bulk to a node having a voltage level (V3) which is equal or close to the voltage level at the input node of the voltage follower.

Abstract: An electronic device comprising circuitry for providing a Power-on-Reset (POR) signal as a function of a supply voltage level of the circuitry. The circuitry comprises a Vbe-cell or a Vgs-cell comprising a first current path including a first transistor and a second current path including a second transistor. Each transistor has a control terminal for controlling a first current in the first current path and a second current in the second current path, wherein a control voltage level is commonly applied to the control terminals of the first and the second transistor. The control voltage level is derived from the current supply voltage level of the circuitry, and the circuitry further comprises a POR output node for providing a POR output signal, which changes from a first state to a second state in response to the ratio of the magnitudes of the first current and the second current.

Abstract: An integrated electronic device includes circuitry for providing a regulated output supply voltage level at an output node from an adjustable current. The circuitry includes an adjustable current source for providing the adjustable current and for adjusting the adjustable current to a magnitude of a target value in response to a configuration signal, an auxiliary adjustable current source providing an auxiliary adjustable current having a magnitude corresponding to the target value, and an output supply voltage level regulating loop coupled to the output node and adapted to keep the output supply voltage level at a preset value. A current selecting stage is adapted to receive the adjustable current and the auxiliary current. The current selecting stage is further adapted to supply a selected current corresponding to a lesser value of the adjustable current and the auxiliary adjustable current.

Abstract: An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current generating stage comprises a crude bias current generator for generating an crude bias current during a power up phase in which at least one of the multiple supply voltages has not yet reached its target supply voltage level, a reference current stage for providing a reference current having a target current value greater than the target value of the crude bias current when the multiple supply voltages have reached their target supply voltage levels. The maximum current selection stage is adapted to continuously output a bias current which is the maximum current of the crude bias current and the reference current.

Abstract: An integrated electronic device includes a sample and hold stage. The sample and hold stage has a sampling capacitor (C) for an input voltage at an input node (Vin), a first switch (S1) coupled between the input node (Vin) and the sampling capacitor (C) for connecting the input node (Vin) to the sampling capacitor (C). There is also a voltage follower with an input coupled to the sampling capacitor (C). The first switch (S1) includes a first MOS transistor (NM1) coupled between the input node (Vin) and the sampling capacitor (C). The first MOS transistor has a bulk. The sample and hold stage is adapted to selectively couple the bulk to a node having a voltage level (V3) which is equal or close to the voltage level at the input node of the voltage follower.

Abstract: Apart from a semiconductor substrate and a photosensitive region in the semiconductor substrate, which comprises a space charge zone region for generating a diffusion current portion and a diffusion region for generating a diffusion current portion, a photodiode includes an insulation means in the semiconductor substrate for at least partially confining the diffusion region against an adjacent surrounding region of the semiconductor substrate.