Abstract: In an embodiment, a circuit comprises: a current regulator configured to selectively couple a first voltage supply to an energy storage device coupled to a load to regulate current through the load; and a voltage regulator configured to selectively couple a charge storage device to the load and to regulate a second voltage supply provided by the charge storage device.

Abstract: A switching current regulator controls a load current flowing through a load. The switching current regulator switches a switch to an ON state after applying a regulating signal to the switch. During an integration period while the switch is in the ON state, the switching current regulator integrates an output voltage based on a sense voltage based on the load current and a reference voltage; at the end of the integration period, the switching current regulator outputs an integrated output voltage. The switching current regulator compares the integrated output voltage to a predetermined value. Based on a result of comparing the integrated output voltage and the predetermined value, the switching current regulator adjusts the regulating signal.

Abstract: A switching current regulator controls a load current flowing through a load. The switching current regulator switches a switch to an ON state after applying a regulating signal to the switch. During an integration period while the switch is in the ON state, the switching current regulator integrates an output voltage based on a sense voltage based on the load current and a reference voltage; at the end of the integration period, the switching current regulator outputs an integrated output voltage. The switching current regulator compares the integrated output voltage to a predetermined value. Based on a result of comparing the integrated output voltage and the predetermined value, the switching current regulator adjusts the regulating signal.

Abstract: A memory device for an error-correcting block code is provided, whereby each code word of the block code can have data bits and parity bits. The device also includes a memory for storing the data bits and the parity bits of each code word, and includes an error detection circuit, which is formed to detect an error of the data bits in a code word by evaluating exactly one subset of the stored parity bits of the code word. The subset being smaller than the total number of parity bits of the code word.

Abstract: A heterogeneous wireless network topology suited for low-power, short-range and ubiquitous ad-hoc communication. The network topology integrates different wireless transmission technologies, in particular to a wireless sensor network including different node types and communication technologies. The network is highly heterogeneous and can be operated according to the master-slave principle. The nodes can have different wireless communication means tailored to their individual role in the network and other constraints, thus allowing different communication patterns.

Abstract: A memory device for an error-correcting block code is provided, whereby each code word of the block code can have data bits and parity bits. The device also includes a memory for storing the data bits and the parity bits of each code word, and includes an error detection circuit, which is formed to detect an error of the data bits in a code word by evaluating exactly one subset of the stored parity bits of the code word. The subset being smaller than the total number of parity bits of the code word.

Abstract: A heterogeneous wireless network topology suited for low-power, short-range and ubiquitous ad-hoc communication. The network topology integrates different wireless transmission technologies, in particular to a wireless sensor network including different node types and communication technologies. The network is highly heterogeneous and can be operated according to the master-slave principle. The nodes can have different wireless communication means tailored to their individual role in the network and other constraints, thus allowing different communication patterns.

Abstract: A pole switch down-converter with symmetric resonator which reduce the non resonating phase to approximately half of the RF carrier period of the modulated signal is proposed. The down-converter comprises a first and second ?/2 resonator for collecting RF energy, wherein a differential RF signal is coupled to the first and second ?/2 resonator, a switching means coupled at one end of the first ?/2 resonator and one end of second ?/2 resonator for connecting the first and second ?/2 resonator, a control means for controlling the switching means, and a detecting means coupled to the first and second ?/2 resonator for detecting the down-converted signal, wherein the control means is adapted to initiate in a down-conversion cycle the switching means to connect the first and second ?/2 resonator for approximate half of the RF carrier period of the modulated signal. With this pole switch down-converter adjacent RF channels can be selected and down-converted by slightly varying the pole switch repetition rate.

Abstract: A pole switch down-converter with symmetric resonator which reduce the non resonating phase to approximately half of the RF carrier period of the modulated signal is proposed. The down-converter comprises a first and second ?/2 resonator for collecting RF energy, wherein a differential RF signal is coupled to the first and second ?/2 resonator, a switching means coupled at one end of the first ?/2 resonator and one end of second ?/2 resonator for connecting the first and second ?/2 resonator, a control means for controlling the switching means, and a detecting means coupled to the first and second ?/2 resonator for detecting the down-converted signal, wherein the control means is adapted to initiate in a down-conversion cycle the switching means to connect the first and second ?/2 resonator for approximate half of the RF carrier period of the modulated signal. With this pole switch down-converter adjacent RF channels can be selected and down-converted by slightly varying the pole switch repetition rate.