Abstract: The invention relates to a method for producing a rewiring printed circuit board with a substrate wafer having passage connections between a first and a second surface. One embodiment of the method comprises applying and patterning masking layers on the first and the second surfaces, thereby uncovering a first contact location on the first surface and a second contact location on the second surface; applying a protective layer to the second surface in order to protect the corresponding masking layer and the second contact location during subsequent method steps; applying a first conductor structure to the first surface, the first conductor structure on the first surface covering the first contact location; removing the protective layer on the second surface; and applying a second conductor structure to the second surface, the second conductor structure on the second surface covering the second contact location.

Abstract: A method of forming a resist layer on a non-planar surface of a substrate includes placing the non-planar surface into an electrophoretic resist. While the non-planar surface is in the electrophoretic resist, an electrical voltage is applied between the substrate and the electrophoretic resist. The non-planar surface can then be removed from the electrophoretic resist.

Abstract: A process is provided for the selective metallization of 3D structures, particularly for the selective gold-plating of 3D contact structures on wafers, such as contact bumps, which are electrically connected to a bond pad on the wafer via a three-dimensional, mechanically flexible structure in the form of a redistribution layer, for subsequent electrical connection to a carrier element, e.g., a printed circuit board. The process is intended to considerably simplify the process sequence. The metallization of the previously prepared 3D structures on the wafer is carried out electrochemically, under current or potential control, by the structures being partially immersed in an electrolyte with a fixed surface. The electrolyte can be covered with a membrane which is permeable to the corresponding ions, or alternatively a gel electrolyte may be used.

Abstract: A conductive connection is made between a semiconductor chip and an external conductor structure. An elevation element is applied on the surface of the semiconductor chip and a soldering island is arranged on the elevation element. An interconnect is produced below the soldering island as far as a bonding island or an I/O pad. Increased reliability of conductive connections of the bonding island or the I/O pad to an external conductive structure can be achieved by preventing the flowing-away of the solder and the oxidation or corrosion of the conductive layer.

Abstract: An arrangement reduces the electrical crosstalk on a chip, in particular between adjacent conductors of the redistribution routing and/or between the redistribution routing on the first passivation on the chip and the metallization of the chip. In one aspect, the arrangement reduces the crosstalk between the redistribution wiring on a chip and its metallization and can be realized simply and independently at the front end. This is achieved by at least an additional conductor (10) being respectively arranged between adjacent conductors of the redistribution routing (1) and/or at least a second passivation (7) with a lower dielectric constant of a preferred “cold dielectric” being arranged between the redistribution routing (1) and the first passivation (2) on the active region of the chip (3).

Abstract: A method is provided for the solder-stop structuring of elevations on wafers, such as 3D contact structures in the form of resilient or compliant contact bumps, which are connected electrically via a metallization layer to a bonding pad on the wafer, the metallization layer extending over the 3D structure and consisting of a Cu/Ni layer which is covered with a Au layer. The present invention provides a method for the solder-stop structuring of elevations on wafers which can be implemented simply and reliably to produce a reliable solder stop and good flank protection of the 3D structure. According to the invention, a resist is deposited on the tip of a 3D structure and a solder stop layer is then deposited over the metallization, including the resist. The resist on the tip of the 3D structure, including the solder stop layer covering the resist, is subsequently removed so that the Au layer on the tip of the 3D structure is exposed.

Abstract: A conductive connection is made between a semiconductor chip and an external conductor structure. An elevation element is applied on the surface of the semiconductor chip and a soldering island is arranged on the elevation element. An interconnect is produced below the soldering island as far as a bonding island or an I/O pad. Increased reliability of conductive connections of the bonding island or the I/O pad to an external conductive structure can be achieved by preventing the flowing-away of the solder and the oxidation or corrosion of the conductive layer.

Abstract: A method of forming a resist layer on a non-planar surface of a substrate includes placing the non-planar surface into an electrophoretic resist. While the non-planar surface is in the electrophoretic resist, an electrical voltage is applied between the substrate and the electrophoretic resist. The non-planar surface can then be removed from the electrophoretic resist.

Abstract: A method is provided for the solder-stop structuring of elevations on wafers, such as 3D contact structures in the form of resilient or compliant contact bumps, which are connected electrically via a metallization layer to a bonding pad on the wafer, the metallization layer extending over the 3D structure and consisting of a Cu/Ni layer which is covered with a Au layer. The present invention provides a method for the solder-stop structuring of elevations on wafers which can be implemented simply and reliably to produce a reliable solder stop and good flank protection of the 3D structure. According to the invention, a resist is deposited on the tip of a 3D structure and a solder stop layer is then deposited over the metallization, including the resist. The resist on the tip of the 3D structure, including the solder stop layer covering the resist, is subsequently removed so that the Au layer on the tip of the 3D structure is exposed.

Abstract: A process is provided for the selective metallization of 3D structures, particularly for the selective gold-plating of 3D contact structures on wafers, such as contact bumps, which are electrically connected to a bond pad on the wafer via a three-dimensional, mechanically flexible structure in the form of a redistribution layer, for subsequent electrical connection to a carrier element, e.g., a printed circuit board. The process is intended to considerably simplify the process sequence. The metallization of the previously prepared 3D structures on the wafer is carried out electrochemically, under current or potential control, by the structures being partially immersed in an electrolyte with a fixed surface. The electrolyte can be covered with a membrane which is permeable to the corresponding ions, or alternatively a gel electrolyte may be used.

Abstract: A photoelectrochemical cell, with a work electrode and a counter electrode that is arranged opposite the work electrode and whose electrochemically active surfaces are facing each other and with an electrolyte being arranged between the surfaces which contains a redox system, with the surface of the counter electrode being catalytically active, is characterized by the fact that the catalytically active surface of the counter electrode contains at least one polymer and/or at least one salt of a polymer, which has been doped to an intrinsically electrically conductive polymer through the redox system of the electrolyte.