Abstract: An apparatus and method for efficient ray tracing. For example, one embodiment of an apparatus comprises: a general purpose processor to generate a plurality of ray streams; a first hardware queue to receive the ray streams generated by the general purpose processor; a graphics processing unit (GPU) comprising a plurality of execution units (EUs) to process the ray streams from the first hardware queue; a second hardware queue to store graphics processing jobs submitted by the GPU; the general purpose processor to process the jobs submitted by the GPU and share results with the GPU.

Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.

Abstract: One embodiment of the present invention sets forth a technique for processing a geometric query. The technique includes determining a tree structure and a set of configurable parameters specified in the geometric query, wherein the set of configurable parameters includes one or more query primitives and one or more search routines. The technique also includes performing one or more operations that traverse the tree structure and execute the one or more search routines to match the one or more query primitives to a first set of geometric objects included in the tree structure. The technique further includes generating a response to the geometric query, wherein the response includes the first set of geometric objects.

Abstract: One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.

Abstract: A compute node performing a distributed light transport simulation operation on a scene may select another compute node(s) for forwarding of a ray based on determining graphical data assigned to the other compute node(s) has already been intersection-tested using the ray. Thus, the compute node can avoid forwarding the ray when the graphical data has already been processed using the ray, while providing flexibility in the partition strategy used to partition the scene amongst the compute nodes. The compute node may receive and/or determine traversal information indicating compute nodes that have already intersection-tested the ray and/or have not yet intersection-tested the ray. The traversal information may include a list of compute nodes that have or have not yet intersection-tested the ray. In some examples, the compute node replays the traversal logic used by the compute nodes to generate one or more portions of the list.

Abstract: One embodiment provides a parallel processor comprising a memory interface and a processing array coupled with the memory interface. The processing array is configured to address memory accessed via the memory interface via a virtual address mapping and includes circuitry to resolve a page fault for the virtual address mapping, wherein each of the multiple compute blocks is separately preemptable.

Abstract: One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.

Abstract: An apparatus and method are described for utilizing volume proxies. For example, one embodiment of an apparatus comprises: a volume subdivision module to subdivide a volume into a plurality of partitions, the apparatus to process a first of the partitions and to distribute data associated with each of the other partitions to each of a plurality of nodes; a proxy generation module to compute a first proxy for the first partition, the first proxy to be transmitted to the plurality of nodes; and a ray tracing engine to perform one or more traversal/intersection operations for a current ray or group of rays using the first proxy; if the ray or group of rays interacts with the first proxy, then the ray tracing engine to send the ray(s) to a second node associated with the first proxy or retrieves data related to the interaction from the second node.

Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.

Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.

Abstract: Approaches presented herein provide for reduction in bandwidth and other resources used for lighting determinations in a rendering process. Sample locations for traced rays in a data volume can be determined by sampling a probability function based on random numbers and density values of macrocells through which those ray pass. Data for the macrocells may be stored and processed using different processors, and there may be no sample locations selected for a given macrocell, such as where the macrocell has a very low maximum density value. If it is determined that no sample locations are contained within a given macrocell through which a ray passes, the ray data is not forwarded to a processor for that macrocell but can instead be forwarded to the processor (if different) for a next macrocell that contains a sample location. Such an approach conserves resources and improves system efficiency by reducing the number of communications and processing operations to be performed.

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.

Abstract: An apparatus and method are described for utilizing volume proxies. For example, one embodiment of an apparatus comprises: a volume subdivision module to subdivide a volume into a plurality of partitions, the apparatus to process a first of the partitions and to distribute data associated with each of the other partitions to each of a plurality of nodes; a proxy generation module to compute a first proxy for the first partition, the first proxy to be transmitted to the plurality of nodes; and a ray tracing engine to perform one or more traversal/intersection operations for a current ray or group of rays using the first proxy; if the ray or group of rays interacts with the first proxy, then the ray tracing engine to send the ray(s) to a second node associated with the first proxy or retrieves data related to the interaction from the second node.

Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.

Abstract: Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

Abstract: One embodiment of the present invention sets forth a technique for generating a bounding volume hierarchy. The technique includes determining a first set of objects associated with a first node. The technique also includes generating a first plurality of child nodes that are associated with the first node. The technique further includes for each object included in the first set of objects, storing within the object an identifier for a corresponding child node included in the first plurality of child nodes based on a first set of partitions associated with the first set of objects.

Abstract: An apparatus and method are described for utilizing volume proxies. For example, one embodiment of an apparatus comprises: a volume subdivision module to subdivide a volume into a plurality of partitions, the apparatus to process a first of the partitions and to distribute data associated with each of the other partitions to each of a plurality of nodes; a proxy generation module to compute a first proxy for the first partition, the first proxy to be transmitted to the plurality of nodes; and a ray tracing engine to perform one or more traversal/intersection operations for a current ray or group of rays using the first proxy; if the ray or group of rays interacts with the first proxy, then the ray tracing engine to send the ray(s) to a second node associated with the first proxy or retrieves data related to the interaction from the second node.

Abstract: Apparatus and method for denoising of images generated by a rendering engine such as a ray tracing engine. For example, one embodiment of a system or apparatus comprises: A system comprising: a plurality of nodes to perform ray tracing operations; a dispatcher node to dispatch graphics work to the plurality of nodes, each node to perform ray tracing to render a region of an image frame; at least a first node of the plurality comprising: a ray-tracing renderer to perform ray tracing to render a first region of the image frame; and a denoiser to perform denoising of the first region using a combination of data associated with the first region and data associated with a region outside of the first region, at least some of the data associated with the region outside of the first region to be retrieved from at least one other node.