Abstract: The present disclosure provides a digital detector apparatus for use with a sensor unit is provided wherein the sensor unit includes an emitter device and a receiver device, the receiver device having a capacitance. The digital detector apparatus comprises at least a first input port, first output port, and a second output port; and an A/D converter circuit wherein an input of the A/D converter circuit is coupled to the first input port for receiving an output of the receiver device; wherein the first output port of the digital detector apparatus is coupled for charging and discharging the capacitance of the receiver device; the second output port of the digital detector apparatus is coupled for driving the emitter device; and the A/D converter circuit derives a sensor output value from the output of the receiver device during a number of charging and discharging cycles. A digital smoke detector and a method of generating an output signal in a digital detector are also provided.

Abstract: The present disclosure provides a digital detector apparatus for use with a sensor unit is provided wherein the sensor unit includes an emitter device and a receiver device, the receiver device having a capacitance. The digital detector apparatus comprises at least a first input port, first output port, and a second output port; and an A/D converter circuit wherein an input of the A/D converter circuit is coupled to the first input port for receiving an output of the receiver device; wherein the first output port of the digital detector apparatus is coupled for charging and discharging the capacitance of the receiver device; the second output port of the digital detector apparatus is coupled for driving the emitter device; and the A/D converter circuit derives a sensor output value from the output of the receiver device during a number of charging and discharging cycles. A digital smoke detector and a method of generating an output signal in a digital detector are also provided.

Abstract: A memory system is provided. In the system, there are first and second sets of dynamic random access memories (DRAMs) and a system register. Each DRAM has at least a first and a second addressable mode register, where the binary address of the second mode register is the inverted binary address of the first mode register. The system register has an input configured to be coupled to a controller, an output coupled to the first set of DRAMs via first address lines and an inverted output coupled to the second set of DRAMs via second address lines. The system register is configured to receive mode register set commands including address bits and configuration bits at the input and to output the mode register set commands non-inverted via the output to the first set of DRAMs and in inverted form via the inverted output to the second set of DRAMs.

Abstract: A memory system is provided. In the system, there are first and second sets of dynamic random access memories (DRAMs) and a system register. Each DRAM has at least a first and a second addressable mode register, where the binary address of the second mode register is the inverted binary address of the first mode register. The system register has an input configured to be coupled to a controller, an output coupled to the first set of DRAMs via first address lines and an inverted output coupled to the second set of DRAMs via second address lines. The system register is configured to receive mode register set commands including address bits and configuration bits at the input and to output the mode register set commands non-inverted via the output to the first set of DRAMs and in inverted form via the inverted output to the second set of DRAMs.